STK16C88-3W45 Cypress Semiconductor Corp, STK16C88-3W45 Datasheet - Page 7

• Manufacturer Part Number: STK16C88-3W45
• Manufacturer: Cypress Semiconductor Corp
• Type: NVSRAMr

Specifications of STK16C88-3W45

• Word Size: 8b
• Organization: 32Kx8
• Density: 256Kb
• Interface Type: Parallel
• Access Time (max): 45ns
• Operating Supply Voltage (typ): 3.3V
• Package Type: PDIP
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Pin Count: 28
• Mounting: Through Hole
• Lead Free Status / Rohs Status: Not Compliant

The AutoStorePlus™ STK16C88-3 is a fast 32K x 8
SRAM that does not lose its data on power-down.
The data is preserved in integral QuantumTrap™
EEPROM
ity of the STK16C88-3 does not require any system
intervention or support: AutoStorePlus™ on power-
down and automatic RECALL on power-up guaran-
tee data integrity without the use of batteries.
NOISE CONSIDERATIONS
Note that the STK16C88-3 is a high-speed memory
and so must have a high-frequency bypass capaci-
tor of approximately 0.1 F connected between V
and V
possible. As with all high-speed
careful routing of power, ground and signals will help
prevent noise problems.
SRAM READ
The STK16C88-3 performs a
E and G are low and W is high. The address speci-
fied on pins A
data bytes will be accessed. When the
ated by an address transition, the outputs will be
valid after a delay of t
READ
at t
The data outputs will repeatedly respond to address
changes within the t
for transitions on any control input pins, and will
remain valid until another address change or until E
or G is brought high.
SRAM WRITE
A
low. The address inputs must be stable prior to
entering the
until either E or W goes high at the end of the cycle.
The data on the common I/O pins DQ
ten into the memory if it is valid t
of a W controlled
E controlled
It is recommended that G be kept high during the
entire
the common I/O lines. If G is left low, internal circuitry
will turn off the output buffers t
February 2002
WRITE
ELQV
SS
is initiated by E or G, the outputs will be valid
WRITE
or at t
, using leads and traces that are as short as
while power is unavailable. The nonvolatil-
cycle is performed whenever E and W are
WRITE
GLQV
WRITE
cycle to avoid data bus contention on
0-14
, whichever is later (
WRITE
determines which of the 32,768
.
AVQV
cycle and must remain stable
AVQV
access time without the need
or t
DVEH
(
READ
WLQZ
READ
before the end of an
DVWH
CMOS
after W goes low.
cycle #1). If the
cycle whenever
READ
DEVICE OPERATION
before the end
0-7
READ
ICs, normal
will be writ-
cycle #2).
is initi-
CC
5-81
AutoStorePlus™ OPERATION
The STK16C88-3’s automatic
down is completely transparent to the system. The
AutoStore™ initiation takes less than 500ns when
power is lost (V
depends only on its internal capacitor for
completion. This safe transfer of data from
EEPROM
slew rate.
In order to prevent unneeded
automatic
one
recent
STORE
or not a
POWER-UP RECALL
During power up, or after any low-power condition
(V
latched. When V
voltage of V
be initiated and will take t
If the STK16C88-3 is in a
power-up
To help avoid this situation, a 10k
be connected either between W and system V
between E and system V
SOFTWARE NONVOLATILE STORE
The STK16C88-3 software
by executing sequential
cific address locations. During the
erase of the previous nonvolatile data is first per-
formed, followed by a program of the nonvolatile
elements. The program operation copies the
data into nonvolatile memory. Once a
is initiated, further input and output are disabled until
the cycle is completed.
Because a sequence of
addresses is used for
tant that no other
vene in the sequence or the sequence will be
aborted and no
To initiate the software
READ
CC
WRITE
< V
sequence must be performed:
STORE
cycles are performed regardless of whether
WRITE
RESET
takes place regardless of power supply
RECALL
STORE
operation has taken place since the most
SWITCH
), an internal
operation has taken place.
or
STORE
CC
, a
CC
s will be ignored unless at least
, the
< V
RECALL
READ
once again exceeds the sense
RECALL
SWITCH
SRAM
STORE
or
STORE
CC
READ
RESTORE
or
RECALL
WRITE
.
) at which point the part
RECALL
STORE
cycle. Softwareinitiated
WRITE
cycle will automatically
READ
data will be corrupted.
initiation, it is impor-
cycles from six spe-
to complete.
cycle, the following
STORE
STORE
state at the end of
STK16C88-3
will take place.
s from specific
cycle is initiated
STORE
accesses inter-
request will be
resistor should
STORE
operations,
on power-
cycle an
SRAM
STORE
SRAM
cycle
CC
or
to