STK16C88-3W45 Cypress Semiconductor Corp, STK16C88-3W45 Datasheet - Page 8

• Manufacturer Part Number: STK16C88-3W45
• Manufacturer: Cypress Semiconductor Corp
• Type: NVSRAMr

Specifications of STK16C88-3W45

• Word Size: 8b
• Organization: 32Kx8
• Density: 256Kb
• Interface Type: Parallel
• Access Time (max): 45ns
• Operating Supply Voltage (typ): 3.3V
• Package Type: PDIP
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Pin Count: 28
• Mounting: Through Hole
• Lead Free Status / Rohs Status: Not Compliant

STK16C88-3
February 2002
The software sequence must be clocked with E
controlled
Once the sixth address in the sequence has been
entered, the
chip will be disabled. It is important that
cycles and not
sequence, although it is not necessary that G be
low for the sequence to be valid. After the t
cycle time has been fulfilled, the
activated for
SOFTWARE NONVOLATILE RECALL
A software
sequence of
to the software
RECALL
operations must be performed:
Internally,
the
1. Read address
2. Read address
3. Read address
4. Read address
5. Read address
6. Read address
1. Read address
2. Read address
3. Read address
4. Read address
5. Read address
6. Read address
SRAM
50
50
40
30
20
10
0
cycle, the following sequence of
data is cleared, and second, the nonvola-
READ
RECALL
READ
STORE
READ
RECALL
Figure 2: I
50
s.
STORE
WRITE
and
is a two-step procedure. First,
operations in a manner similar
0E38 (hex)
31C7 (hex)
03E0 (hex)
3C1F (hex)
303F (hex)
0FC0 (hex)
0E38 (hex)
31C7 (hex)
03E0 (hex)
3C1F (hex)
303F (hex)
0C63 (hex)
cycle will commence and the
Cycle Time (ns)
100
CC
WRITE
cycle is initiated with a
(max) Reads
cycles be used in the
initiation. To initiate the
150
operation.
SRAM
TTL
CMOS
Valid READ
Valid READ
Valid READ
Valid READ
Valid READ
Initiate STORE cycle
Valid READ
Valid READ
Valid READ
Valid READ
Valid READ
Initiate RECALL cycle
200
will again be
READ
READ
STORE
5-82
tile information is transferred into the
After the t
be ready for
RECALL
EEPROM
an unlimited number of times.
HARDWARE PROTECT
The
against inadvertent
WRITE
V
WRITE
LOW AVERAGE ACTIVE POWER
The STK16C88-3 draws significantly less current
when it is cycled at times longer than 55ns. Figure 2
shows the relationship between I
time. Worst-case current consumption is shown for
both
perature range, V
enable). Figure 3 shows the same relationship for
WRITE
than 100%, only standby current is drawn when the
chip is disabled. The overall average current drawn
by the STK16C88-3 depends on the following
items: 1)
cycle of chip enable; 3) the overall cycle rate for
accesses; 4) the ratio of
operating temperature; 6) the V
loading.
SWITCH
CMOS
STK16C88-3
s during low-voltage conditions. When V
s are inhibited.
, all software
40
40
30
30
20
20
10
10
50
cycles. If the chip enable duty cycle is less
0
0
operation in no way alters the data in the
cells. The nonvolatile data can be recalled
RECALL
CMOS
and
Figure 3: I
READ
cycle time the
50
TTL
CC
vs.
= 3.6V, 100% duty cycle on chip
STORE
STORE
input levels (commercial tem-
TTL
offers
and
Cycle Time (ns)
CC
100
(max) Writes
READ
input levels; 2) the duty
WRITE
operations and
operation and
hardware
SRAM
150
s to
CC
TTL
CMOS
CC
level; and 7) I/O
operations. The
and
WRITE
will once again
200
SRAM
READ
protection
s; 5) the
SRAM
SRAM
cells.
cycle
CC
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