IS41LV16105-50KLE ISSI, Integrated Silicon Solution Inc, IS41LV16105-50KLE Datasheet - Page 4

• Manufacturer Part Number: IS41LV16105-50KLE
• Manufacturer: ISSI, Integrated Silicon Solution Inc
• Type: FPMr

Specifications of IS41LV16105-50KLE

• Organization: 1Mx16
• Density: 16Mb
• Address Bus: 10b
• Access Time (max): 50ns
• Operating Supply Voltage (typ): 3.3V
• Package Type: SOJ
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 90mA
• Pin Count: 42
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

IS41C16105
IS41LV16105
Functional Description
The IS41C16105 and IS41LV16105 is a CMOS DRAM
optimized for high-speed bandwidth, low power applica-
tions. During READ or WRITE cycles, each bit is uniquely
addressed through the 16 address bits. These are entered
ten bits (A0-A9) at a time. The row address is latched by
the Row Address Strobe (RAS). The column address is
latched by the Column Address Strobe (CAS). RAS is
used to latch the first nine bits and CAS is used the latter
nine bits.
The IS41C16105 and IS41LV16105 has two CAS con-
trols, LCAS and UCAS. The LCAS and UCAS inputs
internally generates a CAS signal functioning in an iden-
tical manner to the single CAS input on the other 1M x 16
DRAMs. The key difference is that each CAS controls its
corresponding I/O tristate logic (in conjunction with OE
and WE and RAS). LCAS controls I/O0 through I/O7 and
UCAS controls I/O8 through I/O15.
The IS41C16105 and IS41LV16105 CAS function is deter-
mined by the first CAS (LCAS or UCAS) transitioning
LOW and the last transitioning back HIGH. The two CAS
controls give the IS41C16105 and IS41LV16105 both
BYTE READ and BYTE WRITE cycle capabilities.
Memory Cycle
A memory cycle is initiated by bring RAS LOW and it is
terminated by returning both RAS and CAS HIGH. To
ensures proper device operation and data integrity any
memory cycle, once initiated, must not be ended or
aborted before the minimum t
cycle must not be initiated until the minimum precharge
time t
Read Cycle
A read cycle is initiated by the falling edge of CAS or OE,
whichever occurs last, while holding WE HIGH. The
column address must be held for a minimum time speci-
fied by t
t
is dependent on the timing relationships between these
parameters.
4
CAC
and t
RP
, t
AR
OEA
CP
. Data Out becomes valid only when t
has elapsed.
are all satisfied. As a result, the access time
RAS
time has expired. A new
RAC
, t
AA
,
Write Cycle
A write cycle is initiated by the falling edge of CAS and
WE, whichever occurs last. The input data must be valid
at or before the falling edge of CAS or WE, whichever
occurs last.
Refresh Cycle
To retain data, 1,024 refresh cycles are required in each
16 ms period. There are two ways to refresh the memory.
1. By clocking each of the 1,024 row addresses (A0
2. Using a CAS-before-RAS refresh cycle. CAS-before-
CAS-before-RAS is a refresh-only mode and no data
access or device selection is allowed. Thus, the output
remains in the High-Z state during the cycle.
Power-On
After application of the V
200 µs is required followed by a minimum of eight
initialization cycles (any combination of cycles contain-
ing a RAS signal).
During power-on, it is recommended that RAS track with
V
CC
through A9) with RAS at least once every 16 ms. Any
read, write, read-modify-write or RAS-only cycle re-
freshes the addressed row.
RAS refresh is activated by the falling edge of RAS,
while holding CAS LOW. In CAS-before-RAS refresh
cycle, an internal 9-bit counter provides the row ad-
dresses and the external address inputs are ignored.
Integrated Silicon Solution, Inc. — 1-800-379-4774
or be held at a valid V
CC
IH
to avoid current surges.
supply, an initial pause of
ISSI
12/05/05
Rev. B
®