CY7C4282-10ASC Cypress Semiconductor Corp, CY7C4282-10ASC Datasheet
CY7C4282-10ASC
Specifications of CY7C4282-10ASC
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CY7C4282-10ASC Summary of contents
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... In addition, the CY7C4282/92 have an output enable pin (OE). The read and write clocks may be tied together for single-clock operation or the two clocks may be run independently for asynchronous read/write applications ...
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... LD is asserted, WCLK writes data into the programmable flag-offset register. Document #: 38-06009 Rev. *B STQFP Top View CY7C4282 CY7C4292 7C4282/92-10 7C4282/92-15 100 0 CY7C4282 128k x 9 64-pin 10x10 STQFP Description CY7C4282 CY7C4292 GND GND N GND FL/RT N/C 7C4282/92-25 Unit 66.7 40 MHz CY7C4292 Page [+] Feedback ...
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... CMOS technology. Input ESD protection is greater than 2001V, and latch-up is prevented by the use of guard rings. Architecture The CY7C4282/92 consists of an array of 64K to 128K words of 9 bits each (implemented by a dual-port array of SRAM cells), a read pointer, a write pointer, control signals (RCLK, WCLK, REN, WEN, RS), and flags (EF, PAE, PAF, FF). ...
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... Default Value = 007h nized to the LOW-to-HIGH transition of WCLK by one flip-flop and is set LOW when the number of unread words in the FIFO 0 is greater than or equal to CY7C4282 (64K – m) and CY7C4292 (128K – m). PAF is set HIGH by the LOW-to-HIGH (MSB) Default Value = 000h transition of WCLK when the number of available memory locations is greater than m ...
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... A composite flag should be created for each of the end-point status flags (EF and FF). The partial status flags (PAE and PAF) can be detected from any one device. Figure 2 demon- strates a 18-bit word width by using two CY7C4282/92. Any word width can CY7C4282/92 ...
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... Figure 2. Block Diagram of 64K × 9/128K × Deep Sync FIFO Memory Used Document #: 38-06009 Rev. *B RESET (RS) 9 CY7C4282/ FIRST LOAD (FL) EXPANSION IN (XI Width Expansion Configuration CY7C4282 CY7C4292 READ CLOCK (RCLK) READ ENABLE (REN) OUTPUT ENABLE (OE) PROGRAMMABLE (PAF) EMPTY FLAG (EF) EF DATA OUT ( ...
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... Depth Expansion Configuration The CY7C4282/92 can easily be adapted to applications requiring more than 64K/128K words of buffering. Figure 3 shows Depth Expansion using three CY7C4282/92s. Maximum depth is limited only by signal loading. Follow these steps: 1. The first device must be designated by grounding the First Load (FL) control input. ...
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... O CC Com’l 40 Ind 45 Com’l 2 Ind 2 Test Conditions MHz 5.0V CC [10, 11] 3.0V R2 GND 680 3 ns 1.91V CY7C4282 CY7C4292 0. +0.5V CC Ambient Temperature V CC 0°C to +70°C 5V 10% 40°C to +85°C 5V 10% Min. Max. Min. Max. Unit 2.4 2.4 V 0.4 0 ...
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... Almost-Empty Flag and Almost-Full Flag Notes: 12. Pulse widths less than minimum values are not allowed. 13. Values guaranteed by design, not currently tested. Document #: 38-06009 Rev. *B 7C4282/92-10 7C4282/92-15 Min. Max. Min. 100 4 [13 [13 CY7C4282 CY7C4292 7C4282/92-25 Max. Min. Max. Unit 66.7 40 MHz ...
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... CLK t CLKL NO OPERATION t REF VALID DATA t OE [15] t SKEW1 , then FF may not change state until the next WCLK rising edge. SKEW1 , then EF may not change state until the next RCLK rising edge. SKEW2 CY7C4282 CY7C4292 NO OPERATION t WFF REF t OHZ Page [+] Feedback ...
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... The first word is available the cycle after EF goes HIGH, always. Document #: 38-06009 Rev RSS RSR t RSF t RSF t RSF [19] t FRL t REF OLZ When t < minimum specification, t CLK SKEW2 SKEW1 CY7C4282 CY7C4292 [18] OE=1 OE [20 4282–9 (maximum) = either 2 FRL CLK SKEW1 CLK SKEW1 Page [+] Feedback ...
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... DATA IN OUTPUT REGISTER Q – Document #: 38-06009 Rev DATA WRITE 2 t ENS REF REF SKEW1 t A [14 SKEW1 DATA WRITE t WFF t ENS DATA READ CY7C4282 CY7C4292 t ENH [19] t FRL t REF DATA READ NO WRITE DATA WRITE t WFF t ENH t A NEXT DATA READ Page [+] Feedback ...
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... If a read is preformed on this rising edge of the read clock, there will be Empty + (n 1) words in the FIFO when PAE goes LOW 24 write is performed on this rising edge of the write clock, there will be Full 25. 16,384 m words for CY7C4282, 32,768 m words for CY4292. 26 the minimum time between a rising RCLK edge and a rising WCLK edge for PAF to change during that clock cycle. If the time between the rising edge of RCLK and ...
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... Document #: 38-06009 Rev CLKL t ENH t DH PAE OFFSET PAF OFFSET LSB MSB t CLKL t ENH t A UNKNOWN PAE OFFSET LSB t PRT to update these flags. RTR CY7C4282 CY7C4292 PAF OFFSET LSB MSB PAF OFFSET MSB PAF OFFSET PAE OFFSET MSB LSB t RTR . RTR Page [+] Feedback ...
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... Ordering Information 64K x 9 Deep Sync FIFO Speed (ns) Ordering Code 10 CY7C4282-10ASC CY7C4282-10ASI 15 CY7C4282-15ASC 25 CY7C4282-25ASC 128K x 9 Deep Sync FIFO Speed (ns) Ordering Code 10 CY7C4292-10ASC CY7C4292-10ASI 15 CY7C4292-15ASC 25 CY7C4292-25ASC Package Diagram 64-Pin Thin Plastic Quad Flat Pack ( 1.4 mm) A64 All product and company names mentioned in this document are the trademarks of their respective holders. ...
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... Document History Page Document Title: CY7C4282/CY7C4292 64K/128K × 9 Deep Sync FIFOs with Retransmit and Depth Expansion Document Number: 38-06009 REV. ECN NO. Issue Date ** 106470 07/17/01 *A 122261 12/26/02 *B 127855 08/25/03 Document #: 38-06009 Rev. *B Orig. of Change Description of Change SZV Changed from Spec Number: 38-00594 to 38-06009 ...