HI-8282APQI Holt Integrated Circuits, HI-8282APQI Datasheet - Page 5

• Manufacturer Part Number: HI-8282APQI
• Manufacturer: Holt Integrated Circuits

Specifications of HI-8282APQI

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: PQFP
• Rad Hardened: No
• Lead Free Status / Rohs Status: Not Compliant

FUNCTIONAL DESCRIPTION (cont.)
TRANSMITTER
A block diagram of the transmitter section is shown in Figure 3.
FIFO OPERATION
The FIFO is loaded sequentially by first pulsing
and then
the 31 bit word in the next available position of the FIFO. If TX/R,
the transmitter ready flag, is high (FIFO empty), then 8 words,
each 31 bits long, may be loaded. If TX/R is low, then only the
available positions may be loaded. If all 8 positions are full, the
FIFO ignores further attempts to load data.
DATA TRANSMISSION
When ENTX goes high, enabling transmission, the FIFO
positions are incremented with the top register loading into the
data transmission shift register. Within 2.5 data clocks the first
data bit appears at either 429DO or
data transmission shift register are presented sequentially to the
outputs in the ARINC 429 format with the following timing:
The word counter detects when all loaded positions are trans-
mitted and sets the transmitter ready flag, TX/R, high.
TRANSMITTER PARITY
The parity generator counts the ONES in the 31-bit word. If the
ARINC DATA BIT TIME
WORD GAP TIME
PL2
DATA BIT TIME
NULL BIT TIME
to load byte 2. The control logic automatically loads
LOAD SHIFT REGISTER
31 BIT PARALLEL
8 X 31 FIFO
DATA BUS
HIGH SPEED
10 Clocks
40 Clocks
5 Clocks
5 Clocks
429DO
. The 31 bits in the
FIGURE 3. TRANSMITTER BLOCK DIAGRAM
PL1
LOW SPEED
320 Clocks
80 Clocks
40 Clocks
40 Clocks
to load byte 1
HOLT INTEGRATED CIRCUITS
LOAD
BIT CLOCK
ADDRESS
WORD CLOCK
HI-8282A
GENERATOR
5
BIT BD12
PARITY
BD12 control word bit is set low, the 32nd bit transmitted will
make parity odd. If the control bit is high, the parity is even.
SELF TEST
If the BD05 control word bit is set low, 429DO or
internally connected to the receivers inputs, bypassing the
interface circuitry. Data to Receiver 1 is as transmitted and data to
Recevier 2 is the complement. 429DO and
active during self test.
SYSTEM OPERATION
The two receivers are independent of the transmitter. Therefore,
control of data exchanges is strictly at the option of the user. The
only restrictions are:
MASTER RESET (
Upon Master Reset, data transmission and reception are
immediately terminated, the transmit FIFO and receivers
cleared as are the transmit and receive flags. The Control Word
register is not affected by a Master Reset.
within one ARINC word cycle.
Both bytes must be retrieved to clear the data ready flag.
low until TX/R, transmitter ready flag, goes high. Otherwise,
one ARINC word is lost during transmission.
1. The received data may be overwritten if not retrieved
2. The FIFO can store 8 words maximum and ignores
attempts to load addition data if full.
3. Byte 1 of the transmitter data must be loaded first.
4. Either byte of the received data may be retrieved first.
5. After ENTX, transmission enable, goes high it cannot go
CLOCK
DATA
CONTROL BIT BD13
WORD COUNTER
FIFO CONTROL
DATA CLOCK
SEQUENCER
WORD GAP
COUNTER
LOADING
SEQUENCER
DIVIDER
NULL TIMER
DATA AND
MR
AND
FIFO
AND
BIT
)
SEQUENCE
WORD COUNT
INCREMENT
START
429DO
outputs remain
TX CLK
429DO
TX/R
ENTX
PL1
PL2
CLK
429DO
429DO
are