HTRC11001T/02EE,112 NXP Semiconductors, HTRC11001T/02EE,112 Datasheet - Page 12

HTRC11001T/02EE,112

Manufacturer Part Number
HTRC11001T/02EE,112
Description
Manufacturer
NXP Semiconductors
Datasheet

Specifications of HTRC11001T/02EE,112

Operating Supply Voltage (typ)
5V
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
14
Lead Free Status / Rohs Status
Compliant
Philips Semiconductors
8.8.8
?
This command has three functions:
1. Reading back the configuration parameters set by command SET_CONFIG_PAGE
2. Reading back the transmit pulse width programmed with command WRITE_TAG_N
3. Reading the system status information.
Bits P1 and P0 select one of four configuration pages.
The response bits (X3 to X0 and D3 to D0) contains the contents of the selected configuration page in its lower nibble.
For page 0 and page 1 the higher nibble reflects the current setting of the transmit pulse width N.
For page 2 and page 3 the system status information is returned in the higher nibble.
Table 4 Configuration page bit names
Table 5 Description of the configuration page bits
2001 Nov 23
Command bits
Response bits
GET_CONFIG_PAGE 0
GET_CONFIG_PAGE 1
GET_CONFIG_PAGE 2
GET_CONFIG_PAGE 3
D3 to D0
N3 to N0
ANTFAIL
AMPCOMP
HITAG reader chip
BIT NAME
PAGE NUMBER
COMMAND
C
OMMAND
NAME
VALUE
GET_CONFIG_PAGE
XXXX
XXXX
0
1
0
1
contents of the selected configuration page
current setting of the transmit pulse width
antenna failure
no antenna failure
antenna failure
amplitude comparison result (see also bit ACQAMP in Table 3)
actual data signal amplitude is lower than the stored reference
actual data signal amplitude is higher than the stored reference
0 (RFU)
0 (RFU)
BIT 7
X3
0
N3
N3
X3
BIT 6
0 (RFU)
0 (RFU)
X2
0
X2
N2
N2
BIT 5
X1
AMPCOMP
AMPCOMP
0
12
N1
N1
X1
BIT 4
DESCRIPTION
X0
0
BIT
ANTFAIL
ANTFAIL
X0
N0
N0
BIT 3
D3
0
D3
D3
D3
D3
BIT 2
3
D2
1
HTRC11001T
D2
D2
D2
D2
2
Product specification
BIT 1
D1
P1
D1
D1
D1
D1
1
BIT 0
D0
P0
D0
D0
D0
D0
0

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