IS41LV16105C-50KLI ISSI, Integrated Silicon Solution Inc, IS41LV16105C-50KLI Datasheet

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IS41LV16105C-50KLI

Manufacturer Part Number
IS41LV16105C-50KLI
Description
Manufacturer
ISSI, Integrated Silicon Solution Inc
Datasheet

Specifications of IS41LV16105C-50KLI

Lead Free Status / Rohs Status
Compliant
IS41C16105C
IS41LV16105C
1Mx16
16Mb DRAM WITH FAST PAGE MODE
FEATURES
• TTL compatible inputs and outputs; tristate I/O
• Refresh Interval:
• Refresh Mode:
• JEDEC standard pinout
• Single power supply:
• Byte Write and Byte Read operation via two CAS
• Industrial Temperature Range -40
• Lead-free available
Copyright © 2010 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat-
est version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be ex-
pected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon
Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
04/09/2010
— 1,024 cycles/16 ms
— RAS-Only, CAS-before-RAS (CBR), and Hidden
— 5V ± 10% (IS41C16105C)
— 3.3V ± 10% (IS41LV16105C)
o
C to 85
o
C
DESCRIPTION
The
16-bit high-performance CMOS Dynamic Random Access
Memories. Fast Page Mode allows 1,024 random accesses
within a single row with access cycle time as short as 20 ns per
16-bit word. The Byte Write control, of upper and lower byte,
makes the IS41C16105C ideal for use in 16-, 32-bit wide data
bus systems.
These features make the IS41C16105C and IS41LV16105C
ideally suited for high-bandwidth graphics, digital signal
processing, high-performance computing systems, and peripheral
applications.
The IS41C16105C and IS41LV16105C are packaged in a
42-pin 400-mil SOJ and 400-mil 44- (50-) pin TSOP (Type II).
KEY TIMING PARAMETERS
Max. RAS Access Time (t
Max. CAS Access Time (t
Max. Column Address Access Time (t
Min. Fast Page Mode Cycle Time (t
Min. Read/Write Cycle Time (t
Parameter
ISSI
IS41C16105C and IS41LV16105C are 1,048,576 x
rac
cac
ADVANCED INFORMATION
)
)
rc
)
pc
aa
)
APRIL 2010
) 25
-50
50
13
20
84
104
-60
60
15
30
25
Unit
ns
ns
ns
ns
ns
1

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IS41LV16105C-50KLI Summary of contents

Page 1

... These features make the IS41C16105C and IS41LV16105C ideally suited for high-bandwidth graphics, digital signal processing, high-performance computing systems, and peripheral applications. The IS41C16105C and IS41LV16105C are packaged in a 42-pin 400-mil SOJ and 400-mil 44- (50-) pin TSOP (Type II KEY TIMING PARAMETERS Parameter Max ...

Page 2

... IS41C16105C IS41LV16105C PIN CONFIGURATIONS 44(50)-Pin TSOP (Type II) VDD I/ VDD RAS VDD 22 23 PIN DESCRIPTIONS A0-A9 Address Inputs I/O0-15 Data Inputs/Outputs Write Enable WE Output Enable OE Row Address Strobe RAS Upper Column Address Strobe UCAS Lower Column Address Strobe LCAS V Power dd GND Ground NC No Connection 2 42-Pin SOJ GND ...

Page 3

... IS41C16105C IS41LV16105C FUNCTIONAL BLOCK DIAGRAM OE WE CAS LCAS CLOCK UCAS GENERATOR RAS RAS CLOCK GENERATOR REFRESH COUNTER ADDRESS BUFFERS A0-A9 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. 00A 04/09/2010 WE CONTROL CAS WE LOGICS DATA I/O BUS COLUMN DECODERS SENSE AMPLIFIERS MEMORY ARRAY ...

Page 4

... IS41C16105C IS41LV16105C TRUTH TABLE Function Standby Read: Word Read: Lower Byte Read: Upper Byte Write: Word (Early Write) Write: Lower Byte (Early Write) Write: Upper Byte (Early Write) Read-Write (1,2) Hidden Refresh Read (2) Write (1,3) RAS-Only Refresh CBR Refresh (4) Notes: 1. These WRITE cycles may also be BYTE WRITE cycles (either LCAS or UCAS active). 2. These READ cycles may also be BYTE READ cycles (either LCAS or UCAS active). 3. EARLY WRITE only least one of the two CAS signals must be active (LCAS or UCAS). ...

Page 5

... The row address is latched by the Row Address Strobe (RAS). The column address is latched by the Column Address Strobe (CAS). RAS is used to latch the first nine bits and CAS is used the latter nine bits. The IS41C16105C and IS41LV16105C has two CAS controls, LCAS and UCAS. The LCAS and UCAS inputs internally generates a CAS signal functioning in an identi- cal manner to the single CAS input on the other DRAMs. The key difference is that each CAS controls its corresponding I/O tristate logic (in conjunction with OE and WE and RAS) ...

Page 6

... IS41C16105C IS41LV16105C ABSOLUTE MAXIMUM RATINGS Symbol Parameters V Voltage on Any Pin Relative to GND t V Supply Voltage dd I Output Current out P Power Dissipation d T Commercial Temperature a Industrial Temperature T Storage Temperature stg Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. RECOMMENDED OPERATING CONDITIONS Symbol ...

Page 7

... IS41C16105C IS41LV16105C ELECTRICAL CHARACTERISTICS (Recommended Operating Conditions unless otherwise noted.) Symbol Parameter i Standby Current: TTL Standby Current: CMOS Operating Current Random Read/Write (2,3,4) Average Power Supply Current i Operating Current Fast Page Mode (2,3,4) Average Power Supply Current i Refresh Current (2,3) RAS-Only Average Power Supply Current i Refresh Current CBR (2,3,5) Average Power Supply Current Notes initial pause of 200 µs is required after power-up followed by eight RAS refresh cycles (RAS-Only or CBR) before proper device operation is assured. The eight RAS cycles wake-up should be repeated any time the t 2 ...

Page 8

... IS41C16105C IS41LV16105C AC CHARACTERISTICS (1,2,3,4,5,6) (Recommended Operating Conditions unless otherwise noted.) Symbol Parameter t Random READ or WRITE Cycle Time rc t Access Time from RAS rac t Access Time from CAS cac t Access Time from Column-Address aa t RAS Pulse Width ras t RAS Precharge Time rp t (26) CAS Pulse Width cas t CAS Precharge Time (9, 25 CAS Hold Time (21) csh t RAS to CAS Delay Time rcd t Row-Address Setup Time asr t Row-Address Hold Time rah t Column-Address Setup Time asc t Column-Address Hold Time cah t Column-Address Hold Time ar (referenced to RAS) ...

Page 9

... IS41C16105C IS41LV16105C AC CHARACTERISTICS (Continued) (Recommended Operating Conditions unless otherwise noted.) Symbol Parameter t Write Command Hold Time wcr (referenced to RAS) (17) t Write Command Pulse Width Pulse Widths to Disable Outputs wpz t Write Command to RAS Lead Time rwl t Write Command to CAS Lead Time cwl t Write Command Setup Time wcs t Data-in Hold Time (referenced to RAS) dhr t Column-Address Setup Time to CAS ach Precharge during WRITE Cycle t OE Hold Time from WE during oeh READ-MODIFY-WRITE cycle t Data-In Setup Time (15, 22 Data-In Hold Time ...

Page 10

... IS41C16105C IS41LV16105C AC TEST CONDITIONS Output load: Two TTL Loads and One TTL Load and Input timing reference levels 2.4V 2.0V Output timing reference levels Notes initial pause of 200 µs is required after power-up followed by eight RAS refresh cycle (RAS-Only or CBR) before proper device operation is assured. The eight RAS cycles wake-up should be repeated any time the (MIN) and V (MAX) are reference levels for measuring timing of input signals. Transition times, are measured between and V (or between V and V ) and assume for all inputs addition to meeting the transition rate specification, all input signals must transit between monotonic manner CAS and RAS = V , data output is High-Z ...

Page 11

... IS41C16105C IS41LV16105C FAST-PAGE-MODE READ CYCLE RAS t CRP UCAS/LCAS t ASR ADDRESS Row WE I/O OE Note referenced from rising edge of RAS or CAS, whichever occurs last. off Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. 00A 04/09/2010 RAS t CSH t RSH CAS CLCH RCD RAD RAL RAH ASC Column t RCS RAC t CAC ...

Page 12

... IS41C16105C IS41LV16105C FAST PAGE MODE READ-MODIFY-WRITE CYCLE RAS t t CRP RCD UCAS/LCAS RAD t RAH t ASR ADDRESS Row t RCS RAC t CLZ I/O0-I/O15 12 t RASP t CSH t CAS CPWD t CAH t t ASC ASC t Column AR Column t CWL t RWD t t AWD AWD t t CWD CWD t WP ...

Page 13

... IS41C16105C IS41LV16105C FAST-PAGE-MODE EARLY WRITE CYCLE RAS t CRP UCAS/LCAS t ASR ADDRESS Row WE I/O Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. 00A 04/09/2010 (OE = DON'T CARE RAS t CSH t RSH CAS CLCH RCD RAD RAL RAH ASC CAH t ACH Column t CWL t RWL t WCR t t WCS ...

Page 14

... IS41C16105C IS41LV16105C FAST-PAGE-MODE READ WRITE CYCLE RAS t CRP UCAS/LCAS t ASR ADDRESS Row WE I (LATE WRITE and READ-MODIFY-WRITE Cycles) t RWC t RAS t CSH t t CAS RCD RAD RAH CAH ASC Column t RWD t t RCS CWD t AWD RAC t CAC t CLZ Open Valid Integrated Silicon Solution, Inc. — 1-800-379-4774 ...

Page 15

... IS41C16105C IS41LV16105C FAST PAGE MODE EARLY WRITE CYCLE RAS t t CRP RCD UCAS/LCAS RAD t RAH t ASR ADDRESS Row t WCS WE t WCR OE t DHR t DS I/O0-I/O15 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. 00A 04/09/2010 t RASP t t CSH CAS CAS CAH t ASC ...

Page 16

... IS41C16105C IS41LV16105C AC WAVEFORMS READ CYCLE (With WE-Controlled Disable) RAS t CRP UCAS/LCAS t ASR ADDRESS Row WE I/O OE RAS-ONLY REFRESH CYCLE RAS t CRP UCAS/LCAS t ASR ADDRESS I CSH t t RCD CAS RAD t t RAH ASC Column t RCS RAC t CAC t CLZ Open t OE (OE DON'T CARE RAS t RPC t RAH Row Open Integrated Silicon Solution, Inc. — ...

Page 17

... IS41C16105C IS41LV16105C CBR REFRESH CYCLE (Addresses; WE DON'T CARE) RAS t RPC t CP UCAS/LCAS I/O HIDDEN REFRESH CYCLE (1) RAS t CRP UCAS/LCAS t ASR ADDRESS Row I/O OE Notes Hidden Refresh may also be performed after a Write Cycle. In this case LOW and OE = HIGH referenced from rising edge of RAS or CAS, whichever occurs last. off Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. 00A ...

Page 18

... Order Part No. 50 IS41C16105C-50KI IS41C16105C-50KLI IS41C16105C-50TI IS41C16105C-50TLI ORDERING INFORMATION : 3.3V Industrial Range: - Speed (ns) Order Part No. 50 IS41LV16105C-50KI IS41LV16105C-50KLI IS41LV16105C-50TI IS41LV16105C-50TLI Note: The -50 speed option supports 50ns and 60ns timing specifications Package 400-mil SOJ 400-mil SOJ, Lead-free 400-mil TSOP (Type II) 400-mil TSOP (Type II), Lead-free C o Package ...

Page 19

... IS41C16105C IS41LV16105C Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. 00A 04/09/2010 19 ...

Page 20

... IS41C16105C IS41LV16105C 20 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. 00A 04/09/2010 ...

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