ADV612BST Analog Devices Inc, ADV612BST Datasheet - Page 23

• Manufacturer Part Number: ADV612BST
• Manufacturer: Analog Devices Inc

Specifications of ADV612BST

• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temp Range: -25C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 120
• Lead Free Status / Rohs Status: Compliant

Video Formats — Multiplexed Philips Video
The ADV611/ADV612 supports a hybrid mode of operation that
is a cross between standard dual lane Philips and single lane
CCIR-656. In this mode, video data is multiplexed in the same
fashion in CCIR-656, but the values 0 and 255 are not reserved as
signaling values. Instead, external HSYNC and VSYNC pins are
used for signaling and video synchronization. VCLK may range
up to 27 MHz.
VCLK is driven with up to a 27 MHz 50% duty cycle clock
synchronous with the video data. Video data is clocked on the
rising edge of the VCLK signal. The functionality of HSYNC,
VSYNC, and FIELD pins is dependent on three programmable
modes of the ADV611/ADV612; Master-Slave Control, Encode-
Decode Control, and 525-625 Control. Table IX summarizes
the functionality of these pins in various modes.
Video Formats—References
For more information on video interface standards, see the
following reference texts.
• For the definition of CCIR-601:
• For the definition of CCIR-656:
Host Interface
The ADV611/ADV612 host interface is a high performance
interface that passes all command and real-time compressed
video data between the host and codec. A 512 position by 32-bit
wide, bidirectional FIFO buffer passes compressed video data
to and from the host. The host interface is capable of burst
transfer rates of up to 132 million bytes per second (4 33 MHz).
For host interface pins descriptions, see the Pin Function De-
scriptions section. For host interface timing information, see the
Host Interface Timing section.
REV. 0
HSYNC, VSYNC and FIELD
Functionality for Multiplexed
Philips
Encode Mode (video data is input
to the chip)
Decode Mode (video data is output The ADV611/ADV612 completely manages the generation These pins are used to control the
from the chip)
1992 – CCIR Recommendations RBT series Broadcasting Service
(Television) Rec. 601-3 Encoding Parameters of digital television
for studios, page 35, September 15, 1992.
1992 – CCIR Recommendations RBT series Broadcasting Service
(Television) Rec. 656-1 Interfaces for digital component video
signals in 525 and 626 line television systems operating at the
4:2:2 level of Rec. 601, page 46, September 15, 1992.
Table X. Philips Multiplexed Video Master and Slave Modes HSYNC, VSYNC, and FIELD Functionality
Master Mode (HSYNC, VSYNC
and FIELD Are Outputs)
The ADV611/ADV612 completely manages the generation
and timingof these pins. The device driving the ADV611/ blanking of video and sequencing.
ADV612 video interface must use these outputs to remain
in sync with the ADV611/ADV612. It is expected that this
combination of modes would not be used frequently.
and timing of these pins.
–23–
DRAM Manager
The DRAM Manager provides a sorting and reordering func-
tion on the subband coded data between the Wavelet Kernel
and the Programmable Quantizer. The DRAM manager pro-
vides a pipeline delay stage to the ADV611/ADV612. This
pipeline lets the ADV611/ADV612 extract current field image
statistics (min/max pixel values, sum of pixel values, and sum of
squares) used in the calculation of bin widths and reorder
wavelet transform data. The use of current field statistics in the
bin width calculation results in precise control over the com-
pressed bit rate. The DRAM manager manages the entire opera-
tion and refresh of the DRAM.
The interface between the ADV611/ADV612 DRAM man-
ager and DRAM is designed to be transparent to the user. The
ADV611/ADV612 DRAM pins should be connected to the
DRAM as called out in the Pin Function Descriptions section.
The ADV611/ADV612 requires one 256K word by 16-bit,
60 ns DRAM. The following is a selected list of manufacturers
and part numbers. All parts can be used with the ADV611/
ADV612 at all VCLK. Any DRAM used with the ADV611/
ADV612 must meet the minimum specifications outlined for
the Hyper Mode DRAMs listed in Table XI. For DRAM Inter-
face pins descriptions, see the Pin Function Descriptions.
Manufacturer Part Number
Toshiba
NEC
NEC
Hitachi
Table XI. Compatible DRAMs
TC514265DJ/DZ/DFT-60
HM514265CJ-60
PD424210ALE-60
PD42S4210ALE-60
Slave Mode (HSYNC, VSYNC
and FIELD Are Inputs)
These pins are used to control the
blanking of video and sequencing.
ADV611/ADV612
Notes
None
None
CBR Self-Refresh
feature of this
product is not
needed by the
ADV611/ADV612.
None