ADV612BST Analog Devices Inc, ADV612BST Datasheet - Page 41

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ADV612BST

Manufacturer Part Number
ADV612BST
Description
Manufacturer
Analog Devices Inc
Datasheet

Specifications of ADV612BST

Operating Supply Voltage (typ)
5V
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Operating Temp Range
-25C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
120
Lead Free Status / Rohs Status
Compliant

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Price
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Quantity:
205
Parameter
t
t
t
t
t
t
t
t
t
t
NOTES
1
2
3
4
REV. 0
WR input must be asserted (low) until ACK is asserted (low).
Minimum t
Maximum t
During STATS_R deasserted (low) conditions, t
WR_D_WRC
WR_D_PWA
WR_D_PWD
ADR_D_WRS
ADR_D_WRH
DATA_D_WRS
DATA_D_WRH
WR_D_RDT
ACK_D_WRD
ACK_D_WROH
Figure 33. Host (Indirect Address, Indirect Register Data, and Interrupt Mask/Status) Write Transfer Timing
WR_D_RDT
WR_D_WRD
Table XXVII. Host (Indirect Address, Indirect Data and Interrupt Mask/Status) Write Timing Parameters
(I) ADR, BE, CS
varies with VCLK according to the formula: t
(I) DATA
varies with VCLK according to the formula: t
(O) ACK
Description
WR Signal, Direct Register, Write Cycle Time (at 27 MHz VCLK)
WR Signal, Direct Register, Pulsewidth Asserted (at 27 MHz VCLK)
WR Signal, Direct Register, Pulsewidth Deasserted (at 27 MHz VCLK)
ADR Bus, Direct Register, Write Setup
ADR Bus, Direct Register, Write Hold
DATA Bus, Direct Register, Write Setup
DATA Bus, Direct Register, Write Hold
WR Signal, Direct Register, Read Turnaround (After a Write) (at 27 MHz VCLK)
ACK Signal, Direct Register, Write Delay (at 27 MHz VCLK)
ACK Signal, Direct Register, Write Output Hold
(I) WR
(I) RD
ACK_D_WRD
t
t
t
ADR D WRS
DATA D WRS
VALID
ACK D WRD
t
WR D PWA
may be as long as 52 VCLK periods.
WR_D_RDT (MIN)
ACK_D_WRD (MAX)
t
ACK D WROH
VALID
t
t
WR D WRC
t
DATA D WRH
ADR D WRH
–41–
= 0.8 (VCLK Period) +7.4.
= 4.3 (VCLK Period) +14.8.
t
WR D PWD
VALID
VALID
8.6
Min
N/A
N/A
5
2
2
–10
0
35.6
11
ADV611/ADV612
t
WR D RDT
1
1
2
Max
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
182.1
N/A
3, 4
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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