IS42S16800A7TLTR ISSI, Integrated Silicon Solution Inc, IS42S16800A7TLTR Datasheet
IS42S16800A7TLTR
Specifications of IS42S16800A7TLTR
Related parts for IS42S16800A7TLTR
IS42S16800A7TLTR Summary of contents
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... Rev. A 06/01/07 OVERVIEW ISSI 's 128Mb Synchronous DRAM achieves high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input.The 128Mb SDRAM is organized as follows. IS42S16800A 2M x16x4 Banks 54-pin TSOPII KEY TIMING PARAMETERS Parameter -7 Clk Cycle Time ...
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... DD SDRAM read and write accesses are burst oriented starting at a selected location and continuing for a programmed num- ber of locations in a programmed sequence. The registra- tion of an ACTIVE command begins accesses, followed by a READ or WRITE command ...
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IS42S16800A PIN CONFIGURATIONS 54 pin TSOP - Type II for x16 PIN DESCRIPTIONS A0-A11 Row Address Input A0-A8 Column Address Input BA0, BA1 Bank Select Address I/O0 to I/O15 Data I/O CLK System Clock Input CKE Clock Enable CS Chip ...
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... HIGH, disabled. The outputs go to the HIGH impedance state whenDQML/DQMH is HIGH. This function corresponds conventional DRAMs. In write mode,DQML and DQMH control the input buffer. WhenDQML or DQMH is LOW, the corresponding buffer byte is enabled, and data can be written to the device ...
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IS42S16800A GENERAL DESCRIPTION READ The READ command selects the bank from BA0, BA1 inputs and starts a burst read access to an active row. Inputs A0-A8 (x16) provides the starting column location. When A10 is HIGH, this command functions as ...
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IS42S16800A COMMAND TRUTH TABLE CKE Function Symbol n – 1 Device deselect H No operation H Burst stop H Read H Read with auto precharge H Write H Write with auto precharge H Bank activate H Precharge select bank H ...
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IS42S16800A CKE TRUTH TABLE Current State /Function Activating Clock suspend mode entry Any Clock suspend mode Clock suspend mode exit Auto refresh command Idle Self refresh entry Idle Power down entry Idle Deep power down entry Self refresh exit Power ...
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IS42S16800A FUNCTIONAL TRUTH TABLE CS CS RAS RAS CAS CAS RAS RAS RAS CAS CAS CAS Idle ...
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IS42S16800A FUNCTIONAL TRUTH TABLE Continued RAS RAS RAS CAS CAS CAS CAS CS CS RAS RAS CAS Read with auto H × × Precharging Precharge Precharging ...
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IS42S16800A FUNCTIONAL TRUTH TABLE Continued RAS RAS RAS CAS CAS CAS CAS CS CS RAS RAS CAS Write Recovering H × × ...
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IS42S16800A FUNCTIONAL TRUTH TABLE Continued: Notes: 1. All entries assume that CKE is active (CKEn-1=CKEn=H). 2. Illegal to bank in specified states; Function may be legal in the bank indicated by Bank Address (BA), depending on the state of that ...
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IS42S16800A STATE DIAGRAM Mode Register Set DPD Deep Power Down BST Write Write CKE WRITE WRITE SUSPEND CKE CKE WRITEA WRITEA SUSPEND CKE Precharge POWER ON 12 Refresh SELF SELF exit MRS REF IDLE CKE CKE DPD Exit ACT CKE ...
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IS42S16800A ABSOLUTE MAXIMUM RATINGS Symbol Parameters V Maximum Supply Voltage DD MAX V Maximum Supply Voltage for Output Buffer DDQ MAX V Input Voltage IN V Output Voltage OUT P Allowable Power Dissipation D MAX I Output Shorted Current CS ...
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IS42S16800A DC ELECTRICAL CHARACTERISTICS Symbol Parameter I Input Leakage Current IL I Output Leakage Current OL V Output High Voltage Level Output Low Voltage Level OL (1,2) I Operating Current DD1 I Precharge Standby Current DD2P I ...
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IS42S16800A AC ELECTRICAL CHARACTERISTICS Symbol Parameter t Clock Cycle Time CK3 t CK2 (5) t Access Time From CLK AC3 t AC2 t CLK HIGH Level Width CHI t CLK LOW Level Width CL t Output Data Hold Time OH3 ...
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IS42S16800A OPERATING FREQUENCY / LATENCY RELATIONSHIPS SYMBOL PARAMETER — Clock Cycle Time — Operating Frequency t READ/WRITE command to READ/WRITE command CCD t CKE to clock disable or power-down entry mode CKED t CKE to clock enable or power-down exit ...
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IS42S16800A AC TEST CONDITIONS Input Load t CHI 3.0V 1.5V CLK 3.0V INPUT 1. OUTPUT 1.5V AC TEST CONDITIONS Parameter AC High Level Input Voltage/Low Level Input Voltage Input Rise and Fall ...
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... Initialization SDRAMs must be powered up and initialized in a predefined manner. The 128M SDRAM is initialized after the power is applied to V and V (simultaneously) and the clock is stable. DD DDQ A 100µs delay is required prior to issuing any command other than a COMMAND INHIBIT or a NOP ...
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IS42S16800A INITIALIZE AND LOAD MODE REGISTER CLK CKS CKH CKE CMH CMS CMH CMS COMMAND NOP PRECHARGE DQM/ DQML, DQMH A0-A9, A11 ALL BANKS A10 SINGLE BANK BA0, BA1 ALL ...
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IS42S16800A AUTO-REFRESH CYCLE CLK CKS CKH CKE t t CMS CMH COMMAND PRECHARGE NOP DQM/ DQML, DQMH A0-A9, A11 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK ( High-Z ...
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IS42S16800A SELF-REFRESH CYCLE T0 t CLK CKS CKH CKE t t CMS CMH COMMAND PRECHARGE DQM/ DQML, DQMH A0-A9, A11 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK High-Z DQ Precharge all active ...
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... IS42S16800A REGISTER DEFINITION Mode Register The mode register is used to define the specific mode of operation of the SDRAM. This definition includes the selection of a burst length, a burst type, a CAS latency, an operating mode and a write burst mode, as shown in MODE REGISTER DEFINITION. The mode register is programmed via the LOAD MODE REGISTER command and will retain the stored information until it is programmed again or the device loses power ...
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... IS42S16800A BURST LENGTH Read and write accesses to the SDRAM are burst oriented, with the burst length being programmable, as shown in MODE REGISTER DEFINITION. The burst length deter- mines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst ...
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IS42S16800A CAS Latency The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. The latency can be set to two or three clocks. If ...
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... CHIP OPERATION BANK/ROW ACTIVATION Before any READ or WRITE commands can be issued to a bank within the SDRAM, a row in that bank must be “opened.” This is accomplished via the ACTIVE command, which selects both the bank and the row to be activated (see Activating Specific Row Within Specific Bank). ...
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... READ burst, provided that I/O contention can be avoided given system design, there may be a possi- bility that the device driving the input data will go Low-Z before the SDRAM DQs go High-Z. In this case, at least a single-cycle delay should occur between the last read data and the WRITE command. ...
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IS42S16800A same bank. The PRECHARGE command should be is- sued x cycles before the clock edge at which the last desired data element is valid, where x equals the CAS latency minus one. This is shown in the READ to ...
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IS42S16800A RW1 - READ TO WRITE CLK DQM COMMAND ADDRESS DQ RW2 - READ TO WRITE WITH EXTRA CLOCK CYCLE T0 CLK DQM COMMAND READ BANK, ADDRESS COL READ NOP NOP NOP BANK, ...
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IS42S16800A CONSECUTIVE READ BURSTS T0 CLK COMMAND READ BANK, ADDRESS COL n DQ CAS Latency - CLK COMMAND READ NOP BANK, ADDRESS COL n DQ CAS Latency - 3 Integrated Silicon Solution, Inc. — www.issi.com Rev. A ...
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IS42S16800A RANDOM READ ACCESSES T0 CLK COMMAND READ BANK, ADDRESS COL CLK COMMAND READ BANK, ADDRESS COL n DQ CAS Latency - READ READ READ BANK, BANK, BANK, COL b COL m ...
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IS42S16800A READ BURST TERMINATION T0 CLK COMMAND READ BANK a, ADDRESS COL n DQ CAS Latency - CLK COMMAND READ NOP BANK, ADDRESS COL n DQ CAS Latency - 3 Integrated Silicon Solution, Inc. — www.issi.com Rev. ...
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IS42S16800A ALTERNATING BANK READ ACCESSES CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/ DQML, DQMH A0-A9, A11 ROW ENABLE AUTO PRECHARGE A10 ...
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IS42S16800A READ - FULL-PAGE BURST CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP READ t CMS DQM/ DQML, DQMH A0-A9, A11 ROW COLUMN m ...
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IS42S16800A READ - DQM OPERATION CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/ DQML, DQMH A0-A9, A11 ROW ENABLE AUTO PRECHARGE A10 ...
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IS42S16800A READ to PRECHARGE T0 T1 CLK COMMAND READ NOP BANK a, ADDRESS COL n DQ CAS Latency - CLK COMMAND READ NOP BANK, ADDRESS COL n DQ CAS Latency - 3 Integrated Silicon Solution, Inc. — ...
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... An example is shown in WRITE to WRITE diagram. Data either the last of a burst of two or the last desired of a longer burst. The 128Mb SDRAM uses a pipelined architecture and therefore does not require the 2n rule associated with a prefetch architecture. A WRITE command can be initiated on any clock cycle following a previous WRITE command ...
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IS42S16800A WRITE BURST COMMAND ADDRESS WRITE TO WRITE RANDOM WRITE CYCLES COMMAND ADDRESS Integrated Silicon Solution, Inc. — www.issi.com Rev. A 06/01/ CLK WRITE NOP NOP BANK, COL n ...
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IS42S16800A WRITE TO READ T0 CLK COMMAND WRITE BANK, ADDRESS COL Latency = 2 WRITE TO PRECHARGE (TWR @ TCK T0 CLK DQM COMMAND WRITE BANK a, ADDRESS COL ...
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IS42S16800A WRITE to PRECHARGE ( CLK DQM COMMAND WRITE BANK a, ADDRESS COL WRITE Burst Termination COMMAND ADDRESS Integrated Silicon Solution, Inc. — www.issi.com Rev. A 06/01/ 15ns ...
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IS42S16800A WRITE - FULL PAGE BURST CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/DQML DQMH/DQM0 A0-A9, A11 ROW A10 ROW t t ...
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IS42S16800A WRITE - DQM OPERATIOON T0 t CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/DQML DQMH/DQM0 A0-A9, A11 ROW A10 ROW ...
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IS42S16800A ALTERNATING BANK WRITE ACCESS CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP t CMS DQM/DQML DQMH/DQM0 A0-A9, A11 ROW COLUMN ...
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IS42S16800A CLOCK SUSPEND Clock suspend mode occurs when a column access/burst is in progress and CKE is registered LOW. In the clock suspend mode, the internal clock is deactivated, “freezing” the synchronous logic. For each positive clock edge on which ...
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IS42S16800A CLOCK SUSPEND MODE CLK CKS CKH CKS CKE t t CMS CMH COMMAND READ NOP t t CMS CMH DQM/DQML DQMH/DQM0 (2) A0-A9, A11 COLUMN m ...
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IS42S16800A PRECHARGE The PRECHARGE command (see figure) is used to deac- tivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access some specified time (t ...
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IS42S16800A POWER-DOWN MODE CYCLE T0 CLK t t CKS CKH CKE t t CMS CMH COMMAND PRECHARGE DQM/DQML DQMH/DQM0-3 A0-A9, A11 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK High-Z DQ Two clock cycles Precharge all ...
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... CONCURRENT AUTO PRECHARGE An access command (READ or WRITE) to another bank while an access command with auto precharge enabled is executing is not allowed by SDRAMs, unless the SDRAM supports CONCURRENT AUTO PRECHARGE. ISSI SDRAMs support CONCURRENT AUTO PRECHARGE. READ With Auto Precharge interrupted by a READ ...
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IS42S16800A WRITE with Auto Precharge 3. Interrupted by a READ (with or without auto precharge): A READ to bank m will interrupt a WRITE on bank n when registered, with the data-out appearing (CAS latency) later. The PRECHARGE to bank ...
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IS42S16800A SINGLE READ WITH AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/DQML DQMH/DQM0 A0-A9, A11 ROW A10 ROW t t ...
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IS42S16800A READ WITH AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/DQML DQMH/DQM0 A0-A9, A11 ROW ENABLE AUTO PRECHARGE A10 ROW ...
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IS42S16800A SINGLE READ WITHOUT AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/DQML DQMH/DQM0 A0-A9, A11 ROW A10 ROW t t ...
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IS42S16800A READ WITHOUT AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/DQML DQMH/DQM0 A0-A9, A11 ROW A10 ROW t t DISABLE ...
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IS42S16800A SINGLE WRITE WITH AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/DQML DQMH/DQM0 A0-A9, A11 ROW A10 ROW t t ...
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IS42S16800A SINGLE WRITE - WITHOUT AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/DQML DQMH/DQM0 A0-A9, A11 ROW A10 ROW t ...
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IS42S16800A WRITE - WITHOUT AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/DQML DQMH/DQM0 A0-A9, A11 ROW A10 ROW t t ...
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IS42S16800A WRITE - WITH AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP t CMS DQM/DQML DQMH/DQM0 A0-A9, A11 ROW ...
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IS42S16800A ORDERING INFORMATION - V Commercial Range Frequency Speed (ns) Order Part No. 143 MHz 7 IS42S16800A-7T 143 MHz 7 IS42S16800A-7TL 100 MHz 10 IS42S16800A-10T 100 MHz 10 IS42S16800A-10TL Integrated Silicon Solution, Inc. — www.issi.com ...
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PACKAGING INFORMATION Plastic TSOP 54–Pin, 86-Pin Package Code: T (Type II Plastic TSOP (T - Type II) Millimeters Symbol Min Max Ref. Std. No. Leads ( — 1.20 — A1 0.05 0.15 A2 ...