IS43R32400A-6B ISSI, Integrated Silicon Solution Inc, IS43R32400A-6B Datasheet - Page 15

• Manufacturer Part Number: IS43R32400A-6B
• Manufacturer: ISSI, Integrated Silicon Solution Inc
• Type: DDR SDRAMr

Specifications of IS43R32400A-6B

• Organization: 4Mx32
• Density: 128Mb
• Address Bus: 14b
• Access Time (max): 850ps
• Maximum Clock Rate: 166MHz
• Operating Supply Voltage (typ): 2.5V
• Package Type: FBGA
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 2.625V
• Operating Supply Voltage (min): 2.375V
• Supply Current: 420mA
• Pin Count: 144
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Not Compliant

IS43R32400A
BURST LENGTH
The highest access throughput of this device can be
achieved by using a burst of either Read or Write
accesses. The number of accesses in each burst
would be pre-configured to be 2, 4, 8, or full page as
shown in Mode Register Definition (bits M0-M2).
When a Read or Write command is given to the
device, the address bits A0-A7 (x32) select the block
of columns and the starting column for the subsequent
burst. The accesses in this burst can only reference
the selected block, and may wrap-around if a bound-
ary is reached. The Burst Definition table indicates
the relationship between the least significant address
bits and the starting column. The most significant
address bits can select any unique block of columns
in the currently activated row. (Note: Full page bursts
are possible only in Sequential Mode, with the starting
address even.)
BURST DEFINITION
(up to 256)
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00D
02/15/06
Length
Burst
Page
Full
2
4
8
n = A0-A7
address
Starting
A2
0
0
0
0
1
1
1
1
Starting Column
Address
A1
0
0
1
1
0
0
1
0
0
1
1
1
A0
0
1
0
1
0
1
0
1
1
0
1
0
1
0
0
Cn, Cn + 1, Cn + 2
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
Sequential
…Cn - 1,
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
Cn…
0-1
1-0
BURST TYPE
Bursts can be made in either of two types: sequential
or interleaved. The burst type is programmed during a
Load Mode Register command (bit M3). During a
Read or Write burst, the order of accesses is deter-
mined by burst length, starting column, and burst type,
as indicated in the Burst Definition table.
DLL RESET/CLEAR
To cause a DLL reset, the bit M8 is set to 1 in the
Load Mode Register command. When the DLL is
reset, 200 clock cycles are required to occur prior to
any Read operation. To clear the DLL for normal
operation, the bit M8 is set to 0. This device does not
require it, but JEDEC specifications require that any
time that the DLL is reset, it later be cleared prior for
normal operation.
Order of Accesses in a Burst
0-1-2-3-4-5-6-7
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
Not Supported
1-0-3-2-5-4-7-6
Interleaved
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0-1
1-0
ISSI
15
®