IS43LR32160B-6BLI ISSI, Integrated Silicon Solution Inc, IS43LR32160B-6BLI Datasheet

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IS43LR32160B-6BLI

Manufacturer Part Number
IS43LR32160B-6BLI
Description
Manufacturer
ISSI, Integrated Silicon Solution Inc
Datasheet

Specifications of IS43LR32160B-6BLI

Lead Free Status / Rohs Status
Compliant

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Part Number:
IS43LR32160B-6BLI
Manufacturer:
ISSI
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Part Number:
IS43LR32160B-6BLI
Manufacturer:
ISSI, Integrated Silicon Solution Inc
Quantity:
10 000
Rev.00B | Dec. 2010
Description
32 bits. This product uses a double-data-rate architecture to achieve high-speed operation. The Data Input/ Output signals are transmitted
on a 32-bit bus. The double data rate architecture is essentially a 2
words per clock cycle at the I/O pins. This product offers fully synchronous operations referenced to both rising and falling edges of the clock.
The data paths are internally pipelined and 2n-bits prefetched to achieve very high bandwidth. All input and output voltage levels are
compatible with LVCMOS.
Copyright © 2010 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its
products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services
described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information
and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or
malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or
effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to
its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
The IS43/46LR32160B is 536,870,912 bits CMOS Mobile Double Data Rate Synchronous DRAM organized as 4 banks of 4,194,304 words x
Features
• JEDEC standard 1.8V power supply.
• VDD = 1.8V, VDDQ = 1.8V
• Four internal banks for concurrent operation
• MRS cycle with address key programs
• Fully differential clock inputs (CK, /CK)
• All inputs except data & DM are sampled at the rising
• Data I/O transaction on both edges of data strobe
• Bidirectional data strobe per byte of data (DQS)
• DM for write masking only
• Edge aligned data & data strobe output
• Center aligned data & data strobe input
edge of the system clock
- CAS latency 2, 3 (clock)
- Burst length (2, 4, 8, 16)
- Burst type (sequential & interleave)
4M x 32Bits x 4Banks Mobile DDR SDRAM
www.issi.com
N
prefetch architecture with an interface designed to transfer two data
- dram@issi.com
• 64ms refresh period (8K cycle)
• Auto & self refresh
• Concurrent Auto Precharge
• Maximum clock frequency up to 166MHZ
• Maximum data rate up to 333Mbps/pin
• Special Power Saving supports.
• LVCMOS compatible inputs/outputs
• 90-Ball FBGA package
- PASR (Partial Array Self Refresh)
- Auto TCSR (Temperature Compensated Self Refresh)
- Deep Power Down Mode
- Programmable Driver Strength Control by Full Strength
or 1/2, 1/4, 1/8 of Full Strength
IS43LR32160B, IS46LR32160B
Advanced Information
1

Related parts for IS43LR32160B-6BLI

IS43LR32160B-6BLI Summary of contents

Page 1

... Integrated Silicon Solution, Inc is adequately protected under the circumstances Rev.00B | Dec. 2010 IS43LR32160B, IS46LR32160B N prefetch architecture with an interface designed to transfer two data • 64ms refresh period (8K cycle) • ...

Page 2

... DM1 A5 DQ7 DQS1 DQ8 DQ5 DQ9 DQ10 DQ3 DQ11 DQ12 DQ1 DQ13 DQ14 VDDQ DQ15 VSSQ [Top View] www.issi.com - dram@issi.com IS43LR32160B, IS46LR32160B Advanced Information 8 9 DQ16 VDD DQ18 VSSQ DQ20 VDDQ DQ22 VSSQ DQS2 VDDQ DM2 VSS /CAS /RAS BA0 BA1 ...

Page 3

... Data strobe is Strobe used to capture data. Power Supply Power supply Ground Ground DQ Power Supply Power supply for DQ DQ Ground Ground for DQ No Connection No connection. www.issi.com - dram@issi.com IS43LR32160B, IS46LR32160B Advanced Information Descriptions : RA0~RA12 : CA0~CA8 : A10 3 ...

Page 4

... Row 4Mx32 BANK 2 Pre Decoder Column Pre Decoder Column Add Counter Address Burst Register Counter CAS Latency Mode Register www.issi.com - dram@issi.com IS43LR32160B, IS46LR32160B Advanced Information X32 X64 4Mx32 BANK 1 4Mx32 BANK 0 Memory | Cell | Array Column Decoders Data Strobe Transmitter DS Data Strobe ...

Page 5

... Active Power CKEH Down CKEL Row Active WRITE READ A WRITE A READ WRITE PRE WRITE A PRE Precharge PREALL www.issi.com - dram@issi.com IS43LR32160B, IS46LR32160B Advanced Information Self Refresh REFS REFA Refresh CKEL Precharge CKEH Power Down Burst Stop READ BST READ READ A READ A PRE ...

Page 6

... Table 3. Rev.00B | Dec. 2010 CAS Latency M5 M4 CAS Latency Reserved Reserved Reserved Reserved Reserved Reserved www.issi.com - dram@issi.com IS43LR32160B, IS46LR32160B Advanced Information Address Bus Mode Register (Mx) BT Burst Length Burst Type Sequential Interleave Reserved Reserved Reserved Reserved Burst Length Reserved ...

Page 7

... IS43LR32160B, IS46LR32160B Advanced Information Interleave Mode 0-1 1-0 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15 1-0-3-2-5-4-7-6-9-8-11-10-13-12-15-14 2-3-0-1-6-7-4-5-10-11-8-9-14-15-12-13 3-2-1-0-7-6-5-4-11-10-9-8-15-14-13-12 4-5-6-7-0-1-2-3-12-13-14-15-8-9-10-11 5-4-7-6-1-0-3-2-13-12-15-14-9-8-11-10 6-7-4-5-2-3-0-1-14-15-12-13-10-11-8-9 7-6-5-4-3-2-1-0-15-14-13-12-11-10-9-8 8-9-10-11-12-13-14-15-0-1-2-3-4-5-6-7 9-8-11-10-13-12-15-14-1-0-3-2-5-4-7-6 ...

Page 8

... Note: E14(BA1) and E13(BA0) must be set to “1,0” to select Extend Mode Register (vs. the base Mode Register) Rev.00B | Dec. 2010 A10 www.issi.com - dram@issi.com IS43LR32160B, IS46LR32160B Advanced Information Address Bus Extended Mode Register (Ex PASR Self Refresh Coverage Four Banks Two Bank (BA1=0) One Bank (BA1=BA0=0) Reserved Reserved Reserved Reserved Reserved 8 ...

Page 9

... Issue NOP or DESELECT commands for at least tMRD time. 11. The Mobile DDR SDRAM has been properly initialized and is ready to receive any valid command. Rev.00B | Dec. 2010 IS43LR32160B, IS46LR32160B www.issi.com - dram@issi.com Advanced Information ...

Page 10

... NOP PCG AREF AREF All Banks tIS tIH High -Z tCK tRP 4 tRFC 4 Don ’ t care www.issi.com - dram@issi.com IS43LR32160B, IS46LR32160B Advanced Information Tc0 Td0 Te0 MRS MRS ACT tIS tIH CODE CODE RA tIS tIH CODE CODE RA tIS tIH BA0=L, ...

Page 11

... Rev.00B | Dec. 2010 T1 T1n T2 T2n NOP NOP 1tCK tAC CL=2 tRPRE D D OUT OUT n n+1 2tCK tAC CL=3 tRPRE Don ’t care www.issi.com - dram@issi.com IS43LR32160B, IS46LR32160B Advanced Information T3 T3n T4 T4n NOP NOP tRPST D D OUT OUT n+2 n+3 tRPST OUT OUT OUT OUT ...

Page 12

... Thus, during ambient temperatures, the power consumed during refresh was unnecessarily high, because the refresh rate was set to accommodate the higher temperatures. This temperature compensated refresh rate will save power when the DRAM is operating at normal temperatures not supported for any temperature grade with T above +85°C. A Rev.00B | Dec. 2010 IS43LR32160B, IS46LR32160B www.issi.com - dram@issi.com Advanced Information 12 ...

Page 13

... READ or WRITE commands being issued to that bank. A PRECHARGE command will be treated as a NOP if there is no open row in that bank (idle state the previously open row is already in the process of precharging. Rev.00B | Dec. 2010 IS43LR32160B, IS46LR32160B www.issi.com - dram@issi.com Advanced Information ...

Page 14

... This mode is entered by having all banks idle then /CS and /WE held low with /RAS and /CAS held high at the rising edge of the clock, while CKE is low. This mode is exited by asserting CKE high. After applying NOP commands for 200 μs, the Power Up and Initialization sequence must be followed. Rev.00B | Dec. 2010 IS43LR32160B, IS46LR32160B (maximum). To allow for improved efficiency in scheduling and switching REFI > ...

Page 15

... All banks must be precharged before issuing an AUTO-REFRESH or SELF REFRESH command. 10. BA0 and BA1 value select between MRS and EMRS. 11. Used to mask write data, provided coincident with the corresponding data. 12. CKE is HIGH for all commands shown except SELF REFRESH and DEEP POWER-DOWN. Rev.00B | Dec. 2010 IS43LR32160B, IS46LR32160B /CS /RAS /CAS H ...

Page 16

... See the other Truth Tables CKE -1 was the state of CKE at the previous clock edge the result of COMMAND www.issi.com - dram@issi.com IS43LR32160B, IS46LR32160B Advanced Information ACTION n Note Maintain Power Down Maintain Self Refresh Maintain Deep Power Down Exit Power Down 5,6,9 Exit Self Refresh ...

Page 17

... BURST TERMINATE L H READ L L WRITE H L PRECHARGE www.issi.com - dram@issi.com IS43LR32160B, IS46LR32160B Advanced Information n ) Action Continue previous Operation Continue previous Operation Select and activate row Auto refresh Mode register set No action if bank is idle Select Column & start read burst Select Column & start write burst Deactivate Row in bank (or banks) Truncate Read & ...

Page 18

... Not bank-specific. BURST TERMINATE affects the most recent READ burst, regardless of bank. 12. Requires appropriate DM masking. 13. A WRITE command may be applied after the completion of the READ burst; otherwise, a Burst terminate must be used to end the READ prior to asserting a WRITE command. Rev.00B | Dec. 2010 IS43LR32160B, IS46LR32160B www.issi.com - dram@issi.com Advanced Information 18 ...

Page 19

... H ACTIVE READ WRITE PRECHARGE www.issi.com - dram@issi.com IS43LR32160B, IS46LR32160B Advanced Information m ) Action Continue previous Operation Continue previous Operation Any command allowed to bank m Activate Row Start READ burst Start WRITE burst Precharge Activate Row State READ burst Start WRITE burst Precharge Activate Row ...

Page 20

... A WRITE command may be applied after the completion of data output, otherwise a BURST TERMINATE command must be issued to end the READ prior to asserting a WRITE command. Rev.00B | Dec. 2010 n -1 and CKE are HIGH, and after tXSR or tXP has been met if the previous state was Self Refresh or www.issi.com - dram@issi.com IS43LR32160B, IS46LR32160B Advanced Information 20 ...

Page 21

... Symbol Min V (AC) 0.8 x VDDQ VDDQ + 0 (AC) -0.3 0.2 x VDDQ IL V 0.4 x VDDQ 0.6 x VDDQ IX www.issi.com - dram@issi.com IS43LR32160B, IS46LR32160B Advanced Information Rating Unit - -40 ~ 105 - -55 ~ 150 -0.5 ~ 2.7 -0.5 ~ 2.7 50 0.7 Max Unit 1.95 V 1.95 V VDDQ + 0.3 V 0.3 x VDDQ 0.1 x VDDQ ...

Page 22

... IL V TRIP OUTREF C L 1.8V 14.4KΩ Output 20pF Specification 0.9V 0.9V 3V-ns 3V-ns Maximum Amplitude Maximum Amplitude Time [ns] www.issi.com - dram@issi.com IS43LR32160B, IS46LR32160B Advanced Information Symbol Min Max Unit C 1.5 3 1.5 3 3.0 5 3.0 5.0 IO Value Unit 0.8 x VDDQ / 0.2 x VDDQ 0.5 x VDDQ ...

Page 23

... STABLE, data bus inputs are STABLE Address and control inputs are STABLE, data bus inputs are STABLE ≤ 85°C. A ≤ 85°C. A > 85°C: IDD2P, IDD2PS, IDD3PS are deregulated to 2x these values; A www.issi.com - dram@issi.com IS43LR32160B, IS46LR32160B Advanced Information (3, 4) Speed Unit -60 - 0.4 mA ...

Page 24

... IS43LR32160B, IS46LR32160B Advanced Information -75 Unit Note Min Max 7.5 100 2.0 6.0 ns 2.0 8.0 0.45 0.55 tCK 0.45 0.55 tCK 0 ...

Page 25

... XP and T are applicable for all temperature grades with T REF REFI ° C, and these values must be further constrained with T www.issi.com - dram@issi.com IS43LR32160B, IS46LR32160B Advanced Information ∆tDS [ps] ∆tDH [ps +75 +75 +150 +150 ≤ +85°C. Only A2 temperature grade A max of 32ms, and T max of 3.9μs. ...

Page 26

... A0~A12 Don ’t care tCK tCH tCL RD/WT NOP NOP with AP COL Bank a tRCD tRC www.issi.com - dram@issi.com IS43LR32160B, IS46LR32160B Advanced Information Notes : Row address Bank address Ta0 Ta1 ACT NOP ROW Bank b tRRD Ta2 ACT ROW Bank a 26 ...

Page 27

... OUT OUT n n+1 n+2 CL=3 tAC tDQSCK tRPRE tDQSQ D OUT n tLZ tQH Don’t care www.issi.com - dram@issi.com IS43LR32160B, IS46LR32160B Advanced Information Notes : Column address Bank address 3. A10=High : Enable Auto precharge A10=Low : Disable Auto precharge T3n T4 T4n NOP tRPST D OUT n+3 tRPST D D ...

Page 28

... Rev.00B | Dec. 2010 NOP READ NOP Bank a COL m CL OUT OUT n n NOP NOP READ Bank a COL m CL OUT D OUT D OUT www.issi.com - dram@issi.com IS43LR32160B, IS46LR32160B Advanced Information T4 T5 NOP NOP OUT OUT OUT OUT n+2 n NOP NOP NOP OUT D OUT D OUT ...

Page 29

... READ READ READ Bank a Bank a Bank a COL m COL p COL q CL OUT OUT n n BST NOP NOP CL OUT n Don ’ t care www.issi.com - dram@issi.com IS43LR32160B, IS46LR32160B Advanced Information T4 T5 NOP NOP NOP OUT OUT OUT OUT OUT OUT m m+1 p p+1 q q+1 T4 NOP D OUT ...

Page 30

... Shown with nominal tAC, tDQSCK and tDQSQ Rev.00B | Dec. 2010 BST NOP NOP WRITE Bank a COL OUT OUT NOP PCG NOP NOP Bank a (a, or all ) tRP OUT D OUT D OUT www.issi.com - dram@issi.com IS43LR32160B, IS46LR32160B Advanced Information T5 NOP tDQSS (NOM ) ACT Bank a Row D OUT ...

Page 31

... T1n T2 T2n WRITE NOP WRITE Bank a Bank a COL n COL m tDQSS tDQSH tWPRES tWPRE tDS tDH n+1 n+2 n+3 Don ’ t care www.issi.com - dram@issi.com IS43LR32160B, IS46LR32160B Advanced Information Notes : Column address Bank address 3. A10=High : Enable Auto precharge A10=Low : Disable Auto precharge T3 tWPST 31 ...

Page 32

... Din n = Data-In from Column n. 2. Each Write command may be to any banks. Rev.00B | Dec. 2010 NOP WRITE NOP Bank a COL m tDQSS (NOM ) Don’t care NOP NOP WRITE Bank a COL m tDQSS (NOM ) www.issi.com - dram@issi.com IS43LR32160B, IS46LR32160B Advanced Information T4 T5 NOP NOP NOP NOP NOP ...

Page 33

... WRITE WRITE Bank a Bank a Bank a COL p COL m COL q tDQSS (NOM n+1 p p+1 m Don ’t care NOP NOP READ Bank a COL m tWTR n+1 n+2 n+3 www.issi.com - dram@issi.com IS43LR32160B, IS46LR32160B Advanced Information T4 NOP m NOP NOP NOP CL OUT OUT m m+1 D OUT m+2 33 ...

Page 34

... CK edge after the last data-in pair. Rev.00B | Dec. 2010 NOP READ NOP Bank a COL m tWTR CL n NOP READ NOP Bank a COL m tWTR CL=3 www.issi.com - dram@issi.com IS43LR32160B, IS46LR32160B Advanced Information NOP NOP NOP OUT OUT OUT OUT m m+1 m+2 m NOP NOP NOP D ...

Page 35

... Read and Write command can be directed to different banks, in which case tWR is not required and the Read command could be applied ealier. Rev.00B | Dec. 2010 NOP NOP NOP n+1 n+2 n NOP NOP NOP tWR n+1 www.issi.com - dram@issi.com IS43LR32160B, IS46LR32160B Advanced Information T4 T5 NOP PCG tWR T4 T5 PCG NOP 35 ...

Page 36

... CK edge after the last data-in pair. 3. Read and Write command can be directed to different banks, in which case tWR is not required and the Read command could be applied ealier. Rev.00B | Dec. 2010 NOP NOP NOP tWR www.issi.com - dram@issi.com IS43LR32160B, IS46LR32160B Advanced Information T4 T5 PCG NOP 36 ...

Page 37

... Any contents of the mode register be altered by re-programming the mode register through the execution of mode register set command. Figure32 : Mode Resister Set 0 1 /CLK CLK Precharge CMD All Bank Rev.00B | Dec. 2010 CLK /CLK CKE /CS /RAS /CAS /WE A10 Don ’t care Mode Command Resister (any) Set 2 CK min RP www.issi.com - dram@issi.com IS43LR32160B, IS46LR32160B Advanced Information Notes : Bank address ...

Page 38

... T3 T4 tCK tCH tCL VALID NOP NOP AREF tRP tIS tIS AREF Don’t care Self-refresh mode exit www.issi.com - dram@issi.com IS43LR32160B, IS46LR32160B Advanced Information Ta0 Tb0 Ta2 VALID NOP AREF NOP NOP tRFC tRFC Ta1 Tb0 NOP VALID VALID tXSR Tb0 ...

Page 39

... NOP Must not exceed refresh device limits Power-down mode exit T1 T2 Ta0 tIS tCKE DPD Deep Power-down mode entry www.issi.com - dram@issi.com IS43LR32160B, IS46LR32160B Advanced Information Ta1 Tb0 t XP NOP VALID VALID Don ’ t care Ta1 Ta2 Tb 0 T=200us NOP NOP ...

Page 40

... Clock Exit Clock stopped Stop Mode Rev.00B | Dec. 2010 n ; therefore Tn is the last clock pulse required by this Timing Condition CMD NOP NOP Valide (High – Z) Vail Enter Clock Command Stop Mode www.issi.com - dram@issi.com IS43LR32160B, IS46LR32160B Advanced Information NOP Don’t Care 40 ...

Page 41

... Automotive Range, A2: (-40 Configuration Frequency (MHz) 16Mx32 166 133 Rev.00B | Dec. 2010 C) o Speed Order Part No. (ns) 6 IS43LR32160B-6BL 7.5 IS43LR32160B-75BL C) o Speed Order Part No. (ns) 6 IS43LR32160B-6BLI 7.5 IS43LR32160B-75BLI Speed Order Part No. (ns) 6 IS46LR32160B-6BLA1 7.5 IS46LR32160B-75BLA1 C to +105 Speed Order Part No. (ns) 6 IS46LR32160B-6BLA2 7 ...

Page 42

... Rev.00B | Dec. 2010 IS43LR32160B, IS46LR32160B www.issi.com - dram@issi.com Advanced Information 42 ...

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