R8A66173SP#DF0Z Renesas Electronics America, R8A66173SP#DF0Z Datasheet - Page 4

• Manufacturer Part Number: R8A66173SP#DF0Z
• Manufacturer: Renesas Electronics America

Specifications of R8A66173SP#DF0Z

• Pin Count: 14
• Lead Free Status / Rohs Status: Supplier Unconfirmed

R8A66173SP
BLOCK DIAGRAM (EACH CHANNEL)
FUNCTION
The PWM output waveform of each channel is controlled by taking in PWM data from MCU or other device via
serial data input S
12-bit PWM data is input being divided between upper 8-bits (upper byte) and lower 4-bits.
The lower 4-bit data is combined with command data such as channel designation and input as 8-bit data
(lower byte).
The lower byte should be written first, and then the upper byte. Even if only the upper byte is to be changed,
rewrite from the lower byte.
The PWM waveform changes according to the new setting from the next cycle.
One cycle of PWM waveform (=4096 divisions; 12-bit resolution) are divided into 16 (2
subsection consists of 256 (=2
One subsection t consists of an 8-bit PWM waveform (basic waveform). The “H” width of this waveform is
determined according to the upper 8-bits of PWM data. One cycle has 16 subsections t, each of which has
this basic waveform. Among them, those which are designated by the 4-bit-rate multiplier are conditioned to have
a “H” width that is longer by τ. The lower 4-bits of PWM data are used to specify those subsections (tm). The
waveform of other subsections remains unchanged.
The PWM waveform (12-bit resolution) is a combination of two types of waveforms which are different in “H”
width, as described above.
When output control input OC is “H”, the output of every 4-channel turns high-impedance from the next cycle.
When reset input R is “L”, the output of every channel turns high-impedance as soon as the ongoing cycle is
completed, and PWM data of all channels is reset. If R input is changed from “L” to “H”, the next cycle starts,
however, the output of the channels remains high-impedance.
To enable output, rewrite input data for each channel.
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REJ03F0264-0100 Rev.1.00 Jan.24.2008
Page 2 of 12
XIN
: Clock X
S
WR
S
CLK
CS
OC
R
IN
4
5
1
3
2
6
IN
repeat frequency
IN
.
Control
circuit
register
Input
8
; 8-bit resolution) minimum bits τ(=2/f
Low er byte
Upper byte
register
register
To other channels
register
PWM
XIN
PWM circuit
4-bit-rate
multiplier
8-bit
**).
divider
1/2
PWM circuit
Oscillation
12-bit
circuit
4
) subsections t. Each
14
13
12
10
11
8
9
7
Vcc
PWM1
PWM2
PWM3
PWM4
X
X
GND
IN
OUT