R8A66173SP#DF0Z Renesas Electronics America, R8A66173SP#DF0Z Datasheet - Page 7

• Manufacturer Part Number: R8A66173SP#DF0Z
• Manufacturer: Renesas Electronics America

Specifications of R8A66173SP#DF0Z

• Pin Count: 14
• Lead Free Status / Rohs Status: Supplier Unconfirmed

R8A66173SP
PWM Waveform Output
(1)12-bit PWM output
(2)8-bit PWM output
Output Control
(1)Serial data input
(2)Output control input
(3)Reset
Initial State
After power-on, outputs and PWM register data are unstable.
(1)Reset
(2)Serial data input
REJ03F0264-0100 Rev.1.00 Jan.24.2008
Page 5 of 12
One PWM waveform cycle is divided into 16(=2
into 256(=2
determined by the upper 8-bits of PWM data. (In Fig.2 above, ”H” width is 4A
Among these 16 subsections t, subsections tm designated by the lower 4-bits of PWM data have “H”
width that is longer by τ.
(In Fig.2 above, the “H” width of designated 6 subsections (m =2, 4, 6, 10, 12 and 14) is 4B
The “H” width of undesignated subsections remains unchanged.
As explained above, one cycle of waveform is a combination of two waveforms different in the “H” width.
(In Fig. 2 above, one cycle consists of 10 subsections whose “H” width is 74
“H” width is 75
Note: It is impossible to set one whole cycle to “H” level.
As can be seen from the 12-bit PWM waveform output process as described above, 8-bit resolution PWM
waveform can be output by fixing the lower 4-bits of PWM data to 0000
All subsections from t0 to t15 have the “H” width as determined by the upper 8-bits of PWM data.
Note: It is impossible to set one whole cycle to “H” level.
By using data on lower byte register b3 (output control selection bit), output of each channel can be
controlled independently. The state of the selected PWM output changes after the completion of the
ongoing cycle.
When b3 is set 0, lower byte register b0 (write data designation bit) is reset. Do not write on upper byte in
this case.
The status of all 4-channel outputs during a cycle is determined depending on the status of output control
input OC at the start of the cycle. (See Fig. 6.)
Even when output is in a high-impedance state, data on each PWM register is retained, and data can be
rewritten.
When reset input R turns “L”, all operation is reset as soon as the ongoing cycle is completed. The
outputs of all 4-channels turn high-impedance. The PWM register of each channel is reset.
When R is shifted from “L” to “H”, a next cycle starts, and data writing becomes possible. However,
outputs stay in the high-impedance state. (See Fig. 6)
To resume output, write input data for each channel.
Reset input R is kept on “L” level for more than one cycle (2.048ms when f
integrated circuit is put in a reset state.
If stabilization needs more time, e.g. when a quartz resonator is used, keep R on “L” level for an
adequate period of time.
When starting using this integrated circuit without resetting, input false lower byte data (b0=0) to stabilize
lower byte register b0 data, and then input normal data.
8
) minimum resolution bits τ(=2/f
×
τ)
XIN
4
) subsections t, and each subsection is further divided
). The “H” width of subsection t basic waveform is
2.
×
16=
τ and 6 subsections whose
XIN
74
is 4 MHz) or more, this
×
τ)
16=
75
×
τ.)