R8A66173SP#DF0Z Renesas Electronics America, R8A66173SP#DF0Z Datasheet - Page 5

• Manufacturer Part Number: R8A66173SP#DF0Z
• Manufacturer: Renesas Electronics America

Specifications of R8A66173SP#DF0Z

• Pin Count: 14
• Lead Free Status / Rohs Status: Supplier Unconfirmed

R8A66173SP
PIN DESCRIPTIONS
Table 1 Mode Selection
REJ03F0264-0100 Rev.1.00 Jan.24.2008
Page 3 of 12
R
CS
WR
S
S
OC
PWM1∼
PWM4
X
X
IN
CLK
IN
OUT
Pin
(1) Upper byte register
(2) Lower byte register
PWM data setting
(output enable)
Reset input
Chip select input
Write control input
Serial data input
Write clock input
Output control input
PWM outputs 1∼4
Clock input
Clock output
Name
b7
b7
Output disable
Mode
b6
b6
Fig. 1 Upper and Lower Byte Register Makeup
b5
b5
Input/Output
Lower 4-bit data setting
12-bit data setting
Output
Output
Input
Input
Input
Input
Input
Input
Input
b4
b4
"L" : All 4-channels put in high-impedance state.
"L" : Communication with MCU becomes possible. WR, S
enable state.
"L": Serial data written.
"L"-to-"H" edge: Written data stored in upper or lower byte register.
Inputs 8-bit serial data from MCU synchronously with S
Inputs sync clock pulses for 8-bit serial data writing.
"H": All 4-channels put in high-impedance state.
Outputs PWM waveform. (CMOS 3-state output)
Input/output signals generated by clock signal generation circuit.
Oscillation frequency is determined by connecting ceramic or quartz
resonator between X
The frequency of internal clock (PWM timing clock) signals is the 1/2 divider
of the frequency input from clock input X
When external clock signals are used, connect clock generator to X
leave X
b3
b3
b2
b2
OUT
open.
b1
b1
b7
b7
X
b6 b5
b6 b5
X
IN
b0
b0
and X
Lower byte data
X
b4
b4
X
OUT
.
Output control select bit
1
1
0
PWM output "H" w idth setting bits
Write data designation bit
PWM output select bits
PWM output "H" w idth setting bits
Functions
(Upper 8 bits ： b11 ∼ b4)
0 : Low er byte only
1 : Both low er and upper bytes
00 : PWM1
01 : PWM2
10 : PWM3
11 : PWM4
0 : Output disable
(b7 ∼ b4 and b0 are ignored.)
1 : Output enable
(Low er 4 bits ： b3 ∼ b0)
b2 b1
b2 b1
b2 b1
IN
Input serial data
.
X
0
1
b7
b6 b5
CLK
IN
Upper byte data
clock.
and S
b4 b3 b2 b1 b0
−
−
CLK
IN
pin and
put in