72265LA10PF Integrated Device Technology (Idt), 72265LA10PF Datasheet - Page 20

• Manufacturer Part Number: 72265LA10PF
• Description: FIFO Mem Sync Dual Depth/Width Uni-Dir 16K x 18 64-Pin TQFP
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 72265LA10PF

• Package: 64TQFP
• Configuration: Dual
• Bus Directional: Uni-Directional
• Density: 288 Kb
• Organization: 16Kx18
• Data Bus Width: 18 Bit
• Timing Type: Synchronous
• Expansion Type: Depth|Width
• Typical Operating Supply Voltage: 5 V
• Operating Temperature: 0 to 70 °C

NOTES:
1. Retransmit setup is complete after EF returns HIGH, only then can a read operation begin.
2. OE = LOW.
3. W
4. No more than D –2 may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, FF will be HIGH throughout the Retransmit setup procedure.
5. EF goes HIGH at 60 ns + 1 RCLK cycle + t
IDT72255LA/72265LA CMOS SuperSync FIFO™
8,192 x 18 and 16,384 x 18
Q
WCLK
D = 8,192 for IDT72255LA and 16,384 for IDT72265LA.
RCLK
0
WEN
1
REN
PAE
PAF
- Q
= first word written to the FIFO after Master Reset, W
HF
EF
RT
n
t
ENS
W
x
t
A
t
ENH
t
ENS
t
RTS
REF
t
RTS
.
Figure 11. Retransmit Timing (IDT Standard Mode)
2
= second word written to the FIFO after Master Reset.
t
t
t
ENH
REF
HF
t
SKEW4
1
W
x+1
20
2
t
PAF
1
t
ENS
2
t
t
t
A
COMMERCIAL AND INDUSTRIAL
REF
PAE
(5)
TEMPERATURE RANGES
W
1
(3)
JANUARY 13, 2009
t
t
ENH
A
4670 drw 14
W
2
(3)