72265LA10PF Integrated Device Technology (Idt), 72265LA10PF Datasheet - Page 9

• Manufacturer Part Number: 72265LA10PF
• Description: FIFO Mem Sync Dual Depth/Width Uni-Dir 16K x 18 64-Pin TQFP
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 72265LA10PF

• Package: 64TQFP
• Configuration: Dual
• Bus Directional: Uni-Directional
• Density: 288 Kb
• Organization: 16Kx18
• Data Bus Width: 18 Bit
• Timing Type: Synchronous
• Expansion Type: Depth|Width
• Typical Operating Supply Voltage: 5 V
• Operating Temperature: 0 to 70 °C

IDT72255LA/72265LA CMOS SuperSync FIFO™
8,192 x 18 and 16,384 x 18
NOTES:
1. The programming method can only be selected at Master Reset.
2. Parallel reading of the offset registers is always permitted regardless of which programming method has been selected.
3. The programming sequence applies to both IDT Standard and FWFT modes.
17
17
LD
0
0
0
X
1
1
1
12
12
72255LA — 8,192 x 18–BIT
WEN
3FFH if LD is HIGH at Master Reset
3FFH if LD is HIGH at Master Reset
X
0
1
1
1
0
1
07FH if LD is LOW at Master Reset,
07FH if LD is LOW at Master Reset,
EMPTY OFFSET REGISTER
FULL OFFSET REGISTER
DEFAULT VALUE
DEFAULT VALUE
REN
X
1
0
1
1
0
1
Figure 4. Programmable Flag Offset Programming Sequence
Figure 3. Offset Register Location and Default Values
SEN
X
1
1
0
1
X
X
WCLK
X
X
X
X
0
0
9
17
17
RCLK
X
X
X
X
X
13
13
72265LA — 16,384 x 18–BIT
Parallel write to registers:
Empty Offset
Full Offset
Parallel read from registers:
Serial shift into registers:
26 bits for the 72255LA
28 bits for the 72265LA
1 bit for each rising WCLK edge
Starting with Empty Offset (LSB)
Ending with Full Offset (MSB)
No Operation
Write Memory
Read Memory
No Operation
Empty Offset
Full Offset
3FFH if LD is HIGH at Master Reset
3FFH if LD is HIGH at Master Reset
07FH if LD is LOW at Master Reset,
07FH if LD is LOW at Master Reset,
EMPTY OFFSET REGISTER
FULL OFFSET REGISTER
DEFAULT VALUE
DEFAULT VALUE
COMMERCIAL AND INDUSTRIAL
Selection
TEMPERATURE RANGES
JANUARY 13, 2009
4670 drw07
4670 drw06
0
0