MAX5633UCB+D Maxim Integrated Products, MAX5633UCB+D Datasheet - Page 9

• Manufacturer Part Number: MAX5633UCB+D
• Description: IC DAC 16BIT 32CH S&H 64-TQFP
• Manufacturer: Maxim Integrated Products

Specifications of MAX5633UCB+D

• Number Of Bits: 16
• Data Interface: Serial
• Number Of Converters: 32
• Voltage Supply Source: Dual ±
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power Dissipation (max): -
• Settling Time: -

The MAX5631/MAX5632/MAX5633 16-bit digital-to-ana-
log converters (DAC) are composed of two matched
sections. The four MSBs are derived through 15 identi-
cal matched resistors and the lower 12 bits are derived
through a 12-bit inverted R-2R ladder.
The MAX5631/MAX5632/MAX5633 contain 32 buffered
sample/hold circuits with internal hold capacitors.
Internal hold capacitors minimize leakage current,
dielectric absorption, feedthrough, and required board
space. MAX5631/MAX5632/MAX5633 provide a very low
1mV/s droop rate.
The MAX5631/MAX5632/MAX5633 include output buffers
on each channel. The device contains output resistors in
series with the buffer output (Figure 3) for ease of output
filtering and capacitive load driving stability.
Output loads increase the analog supply current (I
and I
Figure 2. Serial Interface Timing Diagram
Table 1. Code Table
SCLK
DIN
CS
MSB
SS
1100 0111 0100 1010
1000 0000 0000 0000
0100 1111 0010 1100
0010 1000 0001 1100
1111 1111 1111 1111
0000 0000 0000 0000
). Excessively loading the outputs drastically
DAC INPUT CODE
t
CSHO
_______________________________________________________________________________________
Sample-and-Hold Amplifiers
Digital-to-Analog Converter
t
Detailed Description
CSSO
LSB
t
DS
B23
t
DH
t
CH
NOMINAL OUTPUT
t
CL
VOLTAGE (V)
B22
-4.0535
9.0535
16-Bit DACs with 32-Channel
6.15
Output
-2.0
2.5
0
DD
Sample-and-Hold Outputs
increases power dissipation. Do not exceed the maxi-
mum power dissipation specified in the Absolute
Maximum Ratings.
The maximum output voltage range depends on the
analog supply voltages available and the output clamp
voltages (see Output Clamp).
The device has a fixed theoretical output range deter-
mined by the reference voltage, gain, and midscale offset.
The output voltage for a given input code is calculated
with the following:
where code is the decimal value of the DAC input
code, V
Full-scale output
Maximum output with V
Midscale output
V
Minimum output with V
Zero-scale output
OUT_
REF
(
V
= 0. All outputs default to this code after power-up
SS
V
(
1.6214 V
B0
OUT
is the reference voltage, and V
+
0 75
.
=
t
CSH1



×
V
65535
t
code
CSS1
)
REF
≤
V
V
SS
REF
DD
OUT
)

 ×

+
= -2.75V
= 8.55V
V
= +2.5V
GS
_
V
≤
REF
(
V
DD
×
-
2 4
5 2428
.
.
V
)
GS
-
is the
9