AD9772AAST Analog Devices Inc, AD9772AAST Datasheet
AD9772AAST
Specifications of AD9772AAST
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AD9772AAST Summary of contents
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FEATURES Single 3 3.5 V supply 14-bit DAC resolution and input data width 160 MSPS input data rate 67.5 MHz reconstruction pass band @ 160 MSPS 74 dBc SFDR @ 25 MHz 2× interpolation filter with high- or ...
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AD9772A TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Product Highlights ........................................................................... 3 Specifications..................................................................................... 4 DC Specifications ......................................................................... 4 Dynamic Specifications ............................................................... 6 Digital Specifications ................................................................... 7 ...
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PRODUCT HIGHLIGHTS 1. A flexible, low power 2× interpolation filter supporting reconstruction bandwidths 67.5 MHz can be configured for a low- or high-pass response with image rejection for traditional baseband or direct IF applications. ...
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AD9772A SPECIFICATIONS DC SPECIFICATIONS AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 0 V, DVDD = 3 MIN MAX Table 1. Parameter RESOLUTION 1 DC ACCURACY Integral Linearity Error (INL) Differential Nonlinearity ...
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Parameter CLKVDD (PLLVDD = 0 V) Voltage Range Clock Supply Current (I ) CLKVDD 5 Nominal Power Dissipation 6 Power Supply Rejection Ratio (PSRR) PSRR − AVDD PSRR − DVDD OPERATING RANGE 1 Measured at I driving a virtual ground. ...
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AD9772A DYNAMIC SPECIFICATIONS AVDD = 3.3 V, CLKVDD = 3.3 V, DVDD = 3.3 V, PLLVDD = 3 MIN MAX output, 50 Ω doubly terminated, unless otherwise noted. Table 2. Parameter DYNAMIC PERFORMANCE Maximum ...
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DIGITAL SPECIFICATIONS AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 0 V, DVDD = 3 MIN MAX Table 3. Parameter DIGITAL INPUTS Logic 1 Voltage Logic 0 Voltage 1 Logic 1 Current ...
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AD9772A DIGITAL FILTER SPECIFICATIONS AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 0 V, DVDD = 3 MIN MAX 50 Ω doubly terminated, unless otherwise noted. Table 4. Parameter MAXIMUM INPUT DATA ...
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ABSOLUTE MAXIMUM RATINGS Table 6. Parameter With Respect to AVDD, DVDD, CLKVDD, ACOM, DCOM, PLLVDD CLKCOM, PLLCOM AVDD, DVDD, CLKVDD, AVDD, DVDD, PLLVDD CLKVDD, PLLVDD ACOM, DCOM, ACOM, DCOM, CLKCOM, PLLCOM CLKCOM, PLLCOM REFIO, REFLO, FSADJ, ACOM SLEEP I , ...
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AD9772A PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Table 8. Pin Function Descriptions Pin No. Mnemonic Description 1, 2, 19, 20 DCOM Digital Common. 3 DB13 Most Significant Data Bit (MSB DB12 to DB1 Data Bit 1 to Data ...
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Pin No. Mnemonic Description 39 REFIO Reference Input/Output. This pin serves as the reference input when the internal reference is disabled (that is, when REFLO is tied to AVDD serves as the 1.2 V reference output when the ...
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AD9772A TERMINOLOGY Linearity Error (Also Called Integral Nonlinearity or INL) Linearity error is defined as the maximum deviation of the actual analog output from the ideal output and is determined by a straight line drawn from zero to full scale. ...
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FROM HP8644A SIGNAL GENERATOR 3.3V 1kΩ 1kΩ CLKVDD CLKCOM AD9772A CLK+ CLK– 1× 1×/2× AWG2021 OR DG2020 EDGE- DIGITAL TRIGGERED DATA EXTERNAL LATCHES CLOCK SLEEP DCOM DVDD 3.3V CH1 HP8130 PULSE GENERATOR CH2 EXTERNAL INPUT CLOCK DISTRIBUTION PLLCLOCK AND MODE ...
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AD9772A TYPICAL PERFORMANCE CHARACTERISTICS AVDD = 3.3 V, CLKDD = 3.3 V, PLLVDD = 0 V, DVDD = 3 IN-BAND OUT-OF-BAND 0 –20 –40 –60 –80 –100 (MHz) OUT Figure 8. Single-Tone ...
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IN-BAND OUT-OF- BAND –20 –40 –60 –80 –100 0 50 100 150 200 f (MHz) OUT Figure 14. Single-Tone Spectral Characteristics @ f with OUT DATA 90 85 0dBFS 80 –6dBFS 75 70 –12dBFS 65 ...
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AD9772A 160MSPS DATA f = 65MSPS DATA DATA –20 –15 –10 A (dBFS) OUT Figure 20. Third-Order IMD Products vs 160MSPS 70 DATA ...
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THEORY OF OPERATION FUNCTIONAL DESCRIPTION Figure 26 shows a simplified block diagram of the AD9772A. The AD9772A is a complete 2× oversampling, 14-bit DAC that includes a 2× interpolation filter, a phase-locked loop (PLL) clock multiplier, and a 1.20 V ...
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AD9772A In many band-limited applications, the images from the reconstruction process must be suppressed by an analog filter following the DAC. The complexity of this analog filter is typically determined by the proximity of the desired fundamental to the first ...
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Zero-Stuffing Option Description As shown in Figure 29, a zero or null in the frequency response (after interpolation and DAC reconstruction) occurs at the final DAC update rate (that is, 2× due to the inherent sin(x)/x DATA roll-off ...
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AD9772A The PLL clock multiplier has two modes of operation. It can be enabled for less demanding applications, providing a reference clock meeting the minimum specified input data rate of 6 MSPS. Alternatively, it can be disabled for applications below ...
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IF applications in which the quarter-wave mixing option is ...
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AD9772A DAC OPERATION The 14-bit DAC, along with the 1.2 V reference and reference control amplifier, is shown in Figure 37. The DAC consists of a large PMOS current source array capable of providing full-scale ...
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OPTIONAL EXTERNAL REF BUFFER REFLO 1.2V REF REFIO ADDITIONAL LOAD 0.1µF FSADJ 2kΩ AD9772A Figure 38. Internal Reference Configuration The internal reference can be disabled by connecting REFLO to AVDD. In this case, an external 1.2 V reference, such as ...
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AD9772A of the output stage and affect the reliability of the AD9772A. The positive output compliance range is slightly dependent on the full-scale output current Operation beyond the OUTFS positive compliance range induces clipping of the output signal, ...
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AD9772A 1kΩ 0.1µF 1kΩ ECL/PECL 0.1µF 1kΩ 0.1µF 1kΩ Figure 44. Differential Clock Interface The quality of the clock and data input signals is important in achieving the optimum performance. The external clock driver circuitry should provide the AD9772A with ...
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AD9772A APPLYING THE AD9772A OUTPUT CONFIGURATIONS The following sections illustrate some typical output configurations for the AD9772A. Unless otherwise noted assumed that I is set to a nominal 20 mA for optimum OUTFS performance. For applications requiring the ...
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R case, R represents the equivalent load resistance seen by LOAD I . The unused output (I ) should be connected directly to OUTA OUTB ACOM. Different values of I and R OUTFS ...
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AD9772A optimum performance. Care should be taken to ensure that the ground plane is uninterrupted over crucial signal paths. On the digital side, this includes the digital input lines running to the DAC. On the analog side, this includes the ...
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APPLICATIONS INFORMATION MULTICARRIER The AD9772A’s wide dynamic range performance makes it well suited for next-generation base station applications in which it reconstructs multiple modulated carriers over a designated fre- quency band. Cellular multicarrier and multimode radios are often referred to ...
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AD9772A BASEBAND SINGLE-CARRIER APPLICATIONS The AD9772A is also well suited for wideband single-carrier applications, such as WCDMA and multilevel quadrature amplitude modulation (QAM), whose modulation scheme requires wide dynamic range from the reconstruction DAC to achieve the out-of-band spectral mask ...
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Regardless of which image is selected for a given application, the adjacent images must be sufficiently filtered. In most cases, a SAW filter providing differential inputs represents the optimum device for this purpose. For single-ended SAW filters, a balanced-to- unbalanced ...
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AD9772A AD9772A EVALUATION BOARD The AD9772A- evaluation board for the AD9772A TxDAC. Careful attention to the layout and circuit design, along with the prototyping area, allows the user to easily and effectively evaluate the AD9772A in different modes ...
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SCHEMATICS ...
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AD9772A AVDD DVDD RED TP14 C7 C8 0.1µF 0.1µF 1 TP15 2 BLK 3 (MSB) DB13 4 DB12 5 DB11 6 DB10 7 DB9 8 DB8 9 DB7 10 DB6 11 DB5 12 DB4 c c DVDD ...
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EVALUATION BOARD LAYOUT Figure 62. Silkscreen Layer—Top Figure 63. Component-Side PCB Layout (Layer 1) Rev Page AD9772A ...
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AD9772A Figure 64. Ground Plane PCB Layout (Layer 2) Figure 65. Power Plane PCB Layout (Layer 3) Rev Page ...
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Figure 66. Solder-Side PCB Layout (Layer 4) Figure 67. Silkscreen Layer—Bottom Rev Page AD9772A ...
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... VIEW A ROTATED 90° CCW ORDERING GUIDE Model Temperature Range AD9772AAST −40°C to +85°C 1 AD9772AASTZ −40°C to +85°C AD9772AASTRL −40°C to +85°C 1 AD9772AASTZRL −40°C to +85°C AD9772A- RoHS Compliant Part. 9.20 9.00 SQ 0.75 1.60 8.80 0.60 MAX 0.45 ...
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NOTES Rev Page AD9772A ...
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AD9772A NOTES ©2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D02253-0-2/08(C) Rev Page ...