ATF1508RE-7AU100 Atmel, ATF1508RE-7AU100 Datasheet - Page 13
![IC CPLD EE 128MC 5NS 100-TQFP](/photos/6/70/67048/313-100-tqfp_sml.jpg)
ATF1508RE-7AU100
Manufacturer Part Number
ATF1508RE-7AU100
Description
IC CPLD EE 128MC 5NS 100-TQFP
Manufacturer
Atmel
Series
ATF1508REr
Specifications of ATF1508RE-7AU100
Programmable Type
In System Programmable (min 10K program/erase cycles)
Delay Time Tpd(1) Max
7.5ns
Voltage Supply - Internal
3 V ~ 3.6 V
Number Of Macrocells
128
Number Of I /o
80
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
100-TQFP, 100-VQFP
Features
Programmable
Voltage
1.8V, 2.5V, 3.3V
Memory Type
EEPROM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Logic Elements/cells
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
6. JTAG-BST/ISP Overview
6.1
3682A–PLD–10/08
JTAG Boundary-scan Cell (BSC) Testing
The JTAG boundary-scan testing is controlled by the Test Access Port (TAP) controller in the
ATF1508RE. The boundary-scan technique involves the inclusion of a shift-register stage (con-
tained in a boundary-scan cell) adjacent to each component so that signals at component
boundaries can be controlled and observed using scan testing methods. Each input pin and I/O
pin has its own boundary-scan cell (BSC) to support boundary-scan testing. The TAP controller
is automatically reset at power-up. The five JTAG modes supported include: SAMPLE/PRE-
LOAD, EXTEST, BYPASS, IDCODE and HIGHZ. The ATF1508RE’s BSC can be fully described
using a BSDL file as described in IEEE 1149.1 standard. This allows ATF1508RE testing to be
described and implemented using any one of the third-party development tools supporting this
standard.
The ATF1508RE also has the option of using the four JTAG-standard I/O pins for ISP. The
ATF1508RE is programmable through the four JTAG pins using the IEEE standard JTAG pro-
gramming protocol established by IEEE 1532 standard using 1.8V/2.5V/3.3V LVCMOS level
programming signals from the ISP interface for in-system programming. The JTAG feature is a
programmable option. If JTAG (BST or ISP) is not needed, then the four JTAG control pins are
available as I/O pins.
The ATF1508RE contains 80 I/O pins and four dedicated input pins. Each input pin and I/O pin
has its own boundary-scan cell (BSC) in order to support boundary-scan testing as described in
detail by IEEE 1532 standard. A typical BSC consists of three capture registers or scan registers
and up to two update registers. There are two types of BSCs, one for input or I/O pin, and one
for the macrocells. The BSCs in the device are chained together through the capture registers.
Input to the capture register chain is fed in from the TDI pin while the output is directed to the
TDO pin. Capture registers are used to capture active device data signals, to shift data in and
out of the device and to load data into the update registers. Control signals are generated inter-
nally by the JTAG TAP controller. The BSC configuration for the input and I/O pins and
macrocells is shown below.
Figure 6-1.
Note:
The ATF1508RE has a pull-up option on TMS and TDI pins. This feature is selected as a design
option.
BSC Configuration for Input and I/O Pins (Except JTAG TAP Pins)
ATF1508RE
13