ATF1508RE-7AU100 Atmel, ATF1508RE-7AU100 Datasheet - Page 6
![IC CPLD EE 128MC 5NS 100-TQFP](/photos/6/70/67048/313-100-tqfp_sml.jpg)
ATF1508RE-7AU100
Manufacturer Part Number
ATF1508RE-7AU100
Description
IC CPLD EE 128MC 5NS 100-TQFP
Manufacturer
Atmel
Series
ATF1508REr
Specifications of ATF1508RE-7AU100
Programmable Type
In System Programmable (min 10K program/erase cycles)
Delay Time Tpd(1) Max
7.5ns
Voltage Supply - Internal
3 V ~ 3.6 V
Number Of Macrocells
128
Number Of I /o
80
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
100-TQFP, 100-VQFP
Features
Programmable
Voltage
1.8V, 2.5V, 3.3V
Memory Type
EEPROM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Logic Elements/cells
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Each of the 128 macrocells generates a buried feedback signal that goes to the global bus (see
Figure
1-3). Each input and I/O pin also feeds into the global bus. The switch matrix in each logic
block then selects 40 individual signals from the global bus. Each macrocell also generates a
foldback logic term that goes to a regional bus. Cascade logic between macrocells in the
ATF1508RE allows fast, efficient generation of complex logic functions. The ATF1508RE con-
tains eight such logic chains, each capable of creating sum term logic with a fan-in of up to 40
product terms.
The ATF1508RE macrocell, shown in
Figure
1-4, is highly flexible and capable of supporting
complex logic functions operating at high speed. The macrocell consists of five sections: product
terms and product term select multiplexer, OR/XOR/CASCADE logic, a flip-flop, output select
and enable, and logic array inputs.
A security fuse, when programmed, protects the contents of the ATF1508RE. Two bytes
(16 bits) of User Electronic Signature are accessible to the user for purposes such as storing
project name, part number, revision or date. The User Electronic Signature is accessible regard-
less of the state of the security fuse.
The ATF1508RE device supports In-System Programming (ISP) via the industry-standard 4-pin
JTAG interface (IEEE 1532 standard), and is fully compliant with IEEE 1149.1 for Boundary
Scan Test. ISP allows the device to be programmed without removing it from the printed circuit
board. In addition to simplifying the manufacturing flow, ISP also allows design modifications to
be made in the field via software.
Figure 1-4.
ATF1508RE Macrocell
BURIED FEEDBACK
SCHMITT
SSTL
TRIGGER
ATF1508RE
6
3682A–PLD–10/08