EPM1270F256C5N Altera, EPM1270F256C5N Datasheet - Page 17

• Manufacturer Part Number: EPM1270F256C5N
• Description: IC MAX II CPLD 1270 LE 256-FBGA
• Manufacturer: Altera
• Series: MAX® IIr

Specifications of EPM1270F256C5N

• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 6.2ns
• Voltage Supply - Internal: 2.5V, 3.3V
• Number Of Logic Elements/blocks: 1270
• Number Of Macrocells: 980
• Number Of I /o: 212
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 256-FBGA
• Voltage: 2.5V, 3.3V
• Memory Type: FLASH
• Number Of Logic Elements/cells: 1270
• Cpld Type: FLASH
• No. Of Macrocells: 980
• No. Of I/o's: 212
• Propagation Delay: 7.5ns
• Global Clock Setup Time: 1.2ns
• Frequency: 304MHz
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• For Use With: 544-2380 - KIT DEV MAXII W/EPM 1270N
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Other names: 544-1336; EPM1270F256C5N

Chapter 2: MAX II Architecture
Logic Elements
Figure 2–7. LE in Normal Mode
Note to
(1) This signal is only allowed in normal mode if the LE is at the end of an adder/subtractor chain.
© October 2008 Altera Corporation
addnsub (LAB Wide)
Figure
data1
data2
data3
cin (from cout
of previous LE)
data4
2–7:
(1)
Normal Mode
The normal mode is suitable for general logic applications and combinational
functions. In normal mode, four data inputs from the LAB local interconnect are
inputs to a four-input LUT (see
selects the carry-in or the data3 signal as one of the inputs to the LUT. Each LE can use
LUT chain connections to drive its combinational output directly to the next LE in the
LAB. Asynchronous load data for the register comes from the data3 input of the LE.
LEs in normal mode support packed registers.
Dynamic Arithmetic Mode
The dynamic arithmetic mode is ideal for implementing adders, counters,
accumulators, wide parity functions, and comparators. An LE in dynamic arithmetic
mode uses four 2-input LUTs configurable as a dynamic adder/subtractor. The first
two 2-input LUTs compute two summations based on a possible carry-in of 1 or 0; the
other two LUTs generate carry outputs for the two chains of the carry-select circuitry.
As shown in
carry-in1 chain. The selected chain’s logic level in turn determines which parallel sum
is generated as a combinational or registered output. For example, when
implementing an adder, the sum output is the selection of two possible calculated
sums:
data1 + data2 + carry in0
or
data1 + data2 + carry-in1
Register Feedback
4-Input
Figure
LUT
Register chain
connection
2–8, the LAB carry-in signal selects either the carry-in0 or
clock (LAB Wide)
(LAB Wide)
ena (LAB Wide)
aclr (LAB Wide)
sload
Figure
(LAB Wide)
sclear
2–7). The Quartus II Compiler automatically
(LAB Wide)
ADATA
ENA
D
ALD/PRE
aload
CLRN
Q
MAX II Device Handbook
Row, column, and
DirectLink routing
Row, column, and
DirectLink routing
Local routing
LUT chain
connection
Register
chain output
2–9