EPM1270F256C5N Altera, EPM1270F256C5N Datasheet - Page 32

• Manufacturer Part Number: EPM1270F256C5N
• Description: IC MAX II CPLD 1270 LE 256-FBGA
• Manufacturer: Altera
• Series: MAX® IIr

Specifications of EPM1270F256C5N

• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 6.2ns
• Voltage Supply - Internal: 2.5V, 3.3V
• Number Of Logic Elements/blocks: 1270
• Number Of Macrocells: 980
• Number Of I /o: 212
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 256-FBGA
• Voltage: 2.5V, 3.3V
• Memory Type: FLASH
• Number Of Logic Elements/cells: 1270
• Cpld Type: FLASH
• No. Of Macrocells: 980
• No. Of I/o's: 212
• Propagation Delay: 7.5ns
• Global Clock Setup Time: 1.2ns
• Frequency: 304MHz
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• For Use With: 544-2380 - KIT DEV MAXII W/EPM 1270N
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Other names: 544-1336; EPM1270F256C5N

2–24
Figure 2–19. MAX II IOE Structure
Note to
(1) Available in EPM1270 and EPM2210 devices only.
I/O Blocks
MAX II Device Handbook
Figure
Data_in
2–19:
Fast_out
The IOEs are located in I/O blocks around the periphery of the MAX II device. There
are up to seven IOEs per row I/O block (5 maximum in the EPM240 device) and up to
four IOEs per column I/O block. Each column or row I/O block interfaces with its
adjacent LAB and MultiTrack interconnect to distribute signals throughout the device.
The row I/O blocks drive row, column, or DirectLink interconnects. The column I/O
blocks drive column interconnects.
Data_out
OE
Drive Strength Control
Programmable
Input Delay
Open-Drain Output
DEV_OE
Slew Control
Optional Schmitt
Trigger Input
Optional
PCI Clamp (1)
V
CCIO
V
CCIO
I/O Pin
Programmable
Pull-Up
© October 2008 Altera Corporation
Optional Bus-Hold
Circuit
Chapter 2: MAX II Architecture
I/O Structure