XC2C256-7VQG100C Xilinx Inc, XC2C256-7VQG100C Datasheet

XC2C256-7VQG100C

Manufacturer Part Number

XC2C256-7VQG100C

Description

IC CR-II CPLD 256MCELL 100-VQFP

Manufacturer

Xilinx Inc

Series

CoolRunner IIr

Datasheets

1.XC2C32A-6QFG32C.pdf (16 pages)

2.XC2C256-7VQG100C.pdf (23 pages)

Specifications of XC2C256-7VQG100C

Programmable Type

In System Programmable

Delay Time Tpd(1) Max

6.7ns

Voltage Supply - Internal

1.7 V ~ 1.9 V

Number Of Logic Elements/blocks

Number Of Macrocells

256

Number Of Gates

6000

Number Of I /o

Operating Temperature

0°C ~ 70°C

Mounting Type

Surface Mount

Package / Case

100-TQFP, 100-VQFP

Features

Programmable

Voltage

1.8V

Memory Type

CMOS

No. Of Macrocells

256

No. Of I/o's

Propagation Delay

5.7ns

Global Clock Setup Time

3.3ns

Frequency

152MHz

Supply Voltage Range

1.7V To 1.9V

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

For Use With

122-1573 - KIT STARTER COOLRUNNER-II LP/LC122-1512 - KIT DESIGN CPLD W/BATT HOLDER

Number Of Logic Elements/cells

Lead Free Status / RoHS Status

Lead free / RoHS Compliant, Lead free / RoHS Compliant

Other names

122-1402

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DS094 (v3.2) March 8, 2007

Features

•

DS094 (v3.2) March 8, 2007

Product Specification

Optimized for 1.8V systems

Industry’s best 0.18 micron CMOS CPLD

Available in multiple package options

Advanced system features

As fast as 5.7 ns pin-to-pin delays

As low as 13 μA quiescent current

Optimized architecture for effective logic synthesis.

Refer to the CoolRunner™-II family data sheet for

architecture description.

Multi-voltage I/O operation — 1.5V to 3.3V

100-pin VQFP with 80 user I/O

144-pin TQFP with 118 user I/O

132-ball CP (0.5mm) BGA with 106 user I/O

208-pin PQFP with 173 user I/O

256-ball FT (1.0mm) BGA with 184 user I/O

Pb-free available for all packages

Fastest in system programming

IEEE1149.1 JTAG Boundary Scan Test

Optional Schmitt-trigger input (per pin)

Unsurpassed low power management

Two separate I/O banks

RealDigital 100% CMOS product term generation

Flexible clocking modes

Global signal options with macrocell control

Advanced design security

PLA architecture

Open-drain output option for Wired-OR and LED

drive

Optional bus-hold, 3-state or weak pull-up on

selected I/O pins

Optional configurable grounds on unused I/Os

Mixed I/O voltages compatible with 1.5V, 1.8V,

2.5V, and 3.3V logic levels

Hot pluggable

All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

1.8V ISP using IEEE 1532 (JTAG) interface

DataGATE enable (DGE) signal control

Optional DualEDGE triggered registers

Clock divider (divide by 2,4,6,8,10,12,14,16)

CoolCLOCK

Multiple global clocks with phase selection per

macrocell

Multiple global output enables

Global set/reset

Superior pinout retention

100% product term routability across function

block

SSTL2-1, SSTL3-1, and HSTL-1 I/O compatibility

www.xilinx.com

XC2C256 CoolRunner-II CPLD

Description

The CoolRunner™-II 256-macrocell device is designed for

both high performance and low power applications. This

lends power savings to high-end communication equipment

and high speed to battery operated devices. Due to the low

power stand-by and dynamic operation, overall system reli-

ability is improved

This device consists of sixteen Function Blocks inter-con-

nected by a low power Advanced Interconnect Matrix (AIM).

The AIM feeds 40 true and complement inputs to each

Function Block. The Function Blocks consist of a 40 by 56

P-term PLA and 16 macrocells which contain numerous

configuration bits that allow for combinational or registered

modes of operation.

Additionally, these registers can be globally reset or preset

and configured as a D or T flip-flop or as a D latch. There

are also multiple clock signals, both global and local product

term types, configured on a per macrocell basis. Output pin

configurations include slew rate limit, bus hold, pull-up,

open drain and programmable grounds. A Schmitt-trigger

input is available on a per input pin basis. In addition to stor-

ing macrocell output states, the macrocell registers may be

configured as "direct input" registers to store signals directly

from input pins.

Clocking is available on a global or Function Block basis.

Three global clocks are available for all Function Blocks as

a synchronous clock source. Macrocell registers can be

individually configured to power up to the zero or one state.

A global set/reset control line is also available to asynchro-

nously set or reset selected registers during operation.

Additional local clock, synchronous clock-enable, asynchro-

nous set/reset and output enable signals can be formed

using product terms on a per-macrocell or per-Function

Block basis.

A DualEDGE flip-flop feature is also available on a per mac-

rocell basis. This feature allows high performance synchro-

nous operation based on lower frequency clocking to help

reduce the total power consumption of the device.

Circuitry has also been included to divide one externally

supplied global clock (GCK2) by eight different selections.

This yields divide by even and odd clock frequencies.

The use of the clock divide (division by 2) and DualEDGE

flip-flop gives the resultant CoolCLOCK feature.

DataGATE is a method to selectively disable inputs of the

CPLD that are not of interest during certain points in time.

Product Specification

Related parts for XC2C256-7VQG100C

XC2C256-7VQG100C Summary of contents

Page 1

... Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. DS094 (v3.2) March 8, 2007 Product Specification 0 XC2C256 CoolRunner-II CPLD Product Specification 0 0 Description The CoolRunner™ ...

Page 2

... LVCMOS standard is used in 3.3V, 2.5V, 1.8V applications. Both HSTL and SSTL I/O standards make use for JEDEC compliance. CoolRunner-II CPLDs are also 1.5V I/O compatible with the use of Schmitt-trigger inputs 1). This device is also Table 1: I/O Standards for XC2C256 IOSTANDARD Attribute LVTTL LVCMOS33 ...

Page 3

... CC CCIO MHz MHz MHz MHz MHz 3.9V IN CCIO 3.9V IN CCIO www.xilinx.com XC2C256 CoolRunner-II CPLD Value Units –0.5 to 2.0 –0.5 to 4.0 –0.5 to 4.0 –0.5 to 4.0 –0.5 to 4.0 –0.5 to 4.0 –65 to +150 °C +150 °C Min Max Units 1.7 1.9 1.7 1.9 3 ...

Page 4

... XC2C256 CoolRunner-II CPLD LVCMOS 3.3V and LVTTL 3.3V DC Voltage Specifications Symbol Parameter V Input source voltage CCIO V High level input voltage IH V Low level input voltage IL V High level output voltage OH V Low level output voltage OL LVCMOS 2.5V DC Voltage Specifications Symbol Parameter ...

Page 5

... Test Conditions - - - – CCIO mA 2.3V OL CCIO , also peak to peak AC noise on V CCIO REF of receiving devices REF www.xilinx.com XC2C256 CoolRunner-II CPLD Min. Max. = 1.4V V – 0.45 - CCIO = 1.4V V – 0.2 - CCIO - 0.4 = 1.4V - 0.2 Min. Max. 1.4 3 CCIO CCIO ...

Page 6

... XC2C256 CoolRunner-II CPLD SSTL3-1 DC Voltage Specifications Symbol Parameter V Input source voltage CCIO (1) V Input reference voltage REF (2) V Termination voltage TT V High level input voltage IH V Low level input voltage IL V High level output voltage OH V Low level output voltage OL Notes: 1 ...

Page 7

... F (1 the maximum external frequency using one p-term while F EXT1 SU1 CO 4. Typical configuration current during T DS094 (v3.2) March 8, 2007 Product Specification Parameter m is approximately 7.7 A. CONFIG www.xilinx.com XC2C256 CoolRunner-II CPLD -6 -7 Min. Max. Min. Max. 1.2 - 1.5 - 1.5 - 2 ...

Page 8

... XC2C256 CoolRunner-II CPLD Internal Timing Parameters ( Symbol Parameter Buffer Delays T Input buffer delay IN T Direct data register input delay DIN T Global Clock buffer delay GCK T Global set/reset buffer delay GSR T Global 3-state buffer delay GTS T Output buffer delay OUT T Output buffer enable/disable delay ...

Page 9

... DIN GCK GSR GTS - OUT , DIN GCK GSR GTS - OUT AC Test Circuit o C Under Test 8 16 DS092_02_092302 PD www.xilinx.com XC2C256 CoolRunner-II CPLD -6 -7 Max. Min. Max. 0.6 - 0.7 1.5 - 3.0 0.8 - 1.0 3.0 - 4.0 0.5 - 0.7 1.2 - 3.0 1.2 - 1.6 3.0 - 4.0 ...

Page 10

... The I/V curve illustrates the nominal amount of current that an I/O can source/sink at different voltage levels 3.3V 2.5V 1.8V 1.5V .5 1.0 1.5 2.0 VO (Output Volts) Figure 4: Typical I/V Curve for XC2C256 www.xilinx.com Iol 2.5 3.0 3.5 XC256_VoIo_all_020703 DS094 (v3.2) March 8, 2007 Product Specification R ...

Page 11

... Bank 208 206 205 203 202 201 200 199 198 197 www.xilinx.com XC2C256 CoolRunner-II CPLD VQ100 CP132 TQ144 PQ208 FT256 136 196 135 195 134 194 193 133 192 6 C6 191 189 - B6 - 188 91 A6 132 187 - C7 - 186 90 B7 131 185 ...

Page 12

... XC2C256 CoolRunner-II CPLD Pin Descriptions (Continued) Function Macro- Block cell VQ100 CP132 TQ144 PQ208 FT256 5(GCK1 5(GCK0 (CDRST 6(GCK2 6(DGE Pin Descriptions (Continued) I/O Function Macro- Bank Block cell www.xilinx.com VQ100 CP132 TQ144 PQ208 FT256 - - - DS094 (v3.2) March 8, 2007 Product Specification ...

Page 13

... G11 2 12 153 B16 2 12 152 D15 151 E14 2 12 150 C16 149 F14 148 F13 147 E15 146 G13 www.xilinx.com XC2C256 CoolRunner-II CPLD VQ100 CP132 TQ144 PQ208 FT256 1 - B10 - - 173 3 - A10 - 174 175 120 - 121 - 124 178 86 B8 125 179 ...

Page 14

... XC2C256 CoolRunner-II CPLD Pin Descriptions (Continued) Function Macro- Block cell VQ100 CP132 TQ144 PQ208 FT256 N13 N14 M12 M13 M14 L12 L13 - P14 P12 M11 N11 - P11 P10 Pin Descriptions (Continued) I/O Function Macro- Bank Block cell 107 R15 1 15 108 ...

Page 15

... R XC2C256 JTAG, Power/Ground, No Connect Pins and Total User I/O Pin Type VQ100 TCK TDI TDO TMS V (JTAG supply CCAUX voltage) Power internal ( Power Bank 1 I 20, 38, 51 CCIO1 Power Bank 2 I CCIO2 Ground 21, 25, 31, 62, 69, 75, 84, 100 No connects Total user I/O DS094 (v3.2) March 8, 2007 ...

Page 16

... XC2C256-7VQ100C 0.5mm XC2C256-6CP132C 0.5mm XC2C256-7CP132C 0.5mm XC2C256-6TQ144C 0.5mm XC2C256-7TQ144C 0.5mm XC2C256-6PQ208C 0.5mm XC2C256-7PQ208C 0.5mm XC2C256-6FT256C 1.0mm XC2C256-7FT256C 1.0mm XC2C256-6VQG100C 0.5mm XC2C256-7VQG100C 0.5mm XC2C256-6CPG132C 0.5mm XC2C256-7CPG132C 0.5mm XC2C256-6TQG144C 0.5mm XC2C256-7TQG144C 0.5mm XC2C256-6PQG208C 0.5mm XC2C256-7PQG208C 0.5mm XC2C256-6FTG256C 1.0mm XC2C256-7FTG256C 1.0mm XC2C256-7VQ100I 0.5mm XC2C256-7CP132I ...

Page 17

... TQ144 7C Part marking for non-chip scale package Figure 5: Sample Package with Part Marking 1. Line 4 = Package code, speed, operating temperature, three digits not related to device part number. Package codes CP132 CPG132. www.xilinx.com XC2C256 CoolRunner-II CPLD Commercia l (C) Package Body Industrial (1) Dimensions I/O ...

Page 18

... XC2C256 CoolRunner-II CPLD I/O (1) 1 I/O (1) 2 I/O ( I/O ( AUX 6 I/O 7 I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 I/O 16 I/O 17 I/O 18 I/O 19 I/O 20 VCCIO1 21 GND 22 I/O (2) 23 I/O (2) 24 I/O (4) 25 GND 18 VQ100 Top View Figure 6: VQ100 Very Thin Quad Flat Pack www ...

Page 19

... I/O I/O I/O I/O I/O I/O I/O I/O TDO VCCIO2 I/O I/O I/O I/O GND Figure 7: CP132 Chip Scale Package www.xilinx.com XC2C256 CoolRunner-II CPLD VCCIO1 I/O I/O I/O I/O TMS I/O GND I/O I/O I/O TCK I/O I/O I/O I/O I/O ...

Page 20

... XC2C256 CoolRunner-II CPLD (1) I/O 2 (1) I/O 3 I/O 4 (1) I/O 5 (1) I AUX 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 I/O 16 I/O 17 I/O 18 I/O 19 I/O 20 I/O 21 I/O 22 I/O 23 I/O 24 I CCIO1 27 I/O 28 GND 29 (2) I/O 30 I/O 31 (2) I/O 32 I/O 33 I/O ...

Page 21

... I/O 47 I/O 48 I/O 49 I/O 50 I/O(4) 51 GND 52 DS094 (v3.2) March 8, 2007 Product Specification PQ208 Top View Figure 9: PQ208 Quad Flat Package www.xilinx.com XC2C256 CoolRunner-II CPLD GND 156 I/O 155 I/O 154 I/O 153 I/O 152 I/O 151 I/O 150 I/O 149 I/O ...

Page 22

... XC2C256 CoolRunner-II CPLD A I/O I/O I/O I/O B I/O I/O I/O I/O C I/O NC I/O I I/O NC I/O E I/O I/O I/O I/O F I/O I/O I/O I/O G I/O I/O I/O I/O H I/O I/O I/O I I/O I/O I/O K I/O I/O I/O VCC L I/O I/O I/O I/O ...

Page 23

... Added Characterization numbers for product release and device part marking 04/02/03 2.1 Updated T 01/26/04 2.2 Updated Device Part Marking. Updated links and Tsol. 02/26/04 2.3 Corrected Theta JC value on XC2C256-7TQ144. 08/03/04 2.4 Pb-free documentation 08/19/04 2.5 Changes to I 10/01/04 2.6 Add Asynchronous Preset/Reset Pulse Width specification to AC Electrical Characteristics. ...

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