XC2C256-7VQG100C Xilinx Inc, XC2C256-7VQG100C Datasheet - Page 3

IC CR-II CPLD 256MCELL 100-VQFP

XC2C256-7VQG100C

Manufacturer Part Number
XC2C256-7VQG100C
Description
IC CR-II CPLD 256MCELL 100-VQFP
Manufacturer
Xilinx Inc
Series
CoolRunner IIr
Datasheets

Specifications of XC2C256-7VQG100C

Programmable Type
In System Programmable
Delay Time Tpd(1) Max
6.7ns
Voltage Supply - Internal
1.7 V ~ 1.9 V
Number Of Logic Elements/blocks
16
Number Of Macrocells
256
Number Of Gates
6000
Number Of I /o
80
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
100-TQFP, 100-VQFP
Features
Programmable
Voltage
1.8V
Memory Type
CMOS
No. Of Macrocells
256
No. Of I/o's
80
Propagation Delay
5.7ns
Global Clock Setup Time
3.3ns
Frequency
152MHz
Supply Voltage Range
1.7V To 1.9V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
122-1573 - KIT STARTER COOLRUNNER-II LP/LC122-1512 - KIT DESIGN CPLD W/BATT HOLDER
Number Of Logic Elements/cells
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
122-1402

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Absolute Maximum Ratings
DC Electrical Characteristics
DS094 (v3.2) March 8, 2007
Product Specification
Notes:
1.
2.
3.
Notes:
1.
2.
Recommended Operating Conditions
I
I
I
C
C
C
I
I
CCSB
CCSB
CC
IL
IH
Symbol
JTAG
CLK
IO
(2)
(2)
Symbol
V
Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easiest to achieve. During transitions,
the device pins may undershoot to –2.0v or overshoot to +4.5V, provided this over or undershoot lasts less than 10 ns and with the
forcing current being limited to 200 mA.
Valid over commercial temperature range.
For soldering guidelines and thermal considerations, see the
packages, see XAPP427.
16-bit up/down, resettable binary counter (one counter per function block) tested at
See Quality and Reliability section of the CoolRunner-II family data sheet
Symbol
V
V
V
T
CCAUX
V
V
V
V
JTAG
CCIO
CCAUX
STG
V
CC
CCIO
TS
IN
T
CC
J
(1)
(1)
(3)
(2)
R
Standby current Commercial
Standby current Industrial
Dynamic current
JTAG input capacitance
Global clock input capacitance
I/O capacitance
Input leakage current
I/O High-Z leakage
Supply voltage for internal logic
and input buffers
Supply voltage for output drivers @ 3.3V operation
Supply voltage for output drivers @ 2.5V operation
Supply voltage for output drivers @ 1.8V operation
Supply voltage for output drivers @ 1.5V operation
JTAG programming
Supply voltage relative to ground
Supply voltage for output drivers
JTAG input voltage limits
JTAG input supply voltage
Input voltage relative to ground
Voltage applied to 3-state output
Storage Temperature (ambient)
Junction Temperature
Parameter
(Over Recommended Operating Conditions)
Description
Parameter
V
V
IN
IN
V
V
www.xilinx.com
CC
CC
Commercial T
Industrial T
= 0V or V
= 0V or V
Test Conditions
= 1.9V, V
= 1.9V, V
Device Packaging
f = 50 MHz
f = 1 MHz
f = 1 MHz
f = 1 MHz
f = 1 MHz
CCIO
CCIO
A
CCIO
CCIO
= –40°C to +85°C
A
to 3.9V
to 3.9V
= 0°C to +70°C
= 3.6V
= 3.6V
information on the Xilinx website. For Pb free
V
CC
= V
Typical
33
54
CCIO
-
-
-
-
-
-
-
XC2C256 CoolRunner-II CPLD
–65 to +150
Min
–0.5 to 2.0
–0.5 to 4.0
–0.5 to 4.0
–0.5 to 4.0
–0.5 to 4.0
–0.5 to 4.0
1.7
1.7
3.0
2.3
1.7
1.4
1.7
= 1.9V
Value
+150
Max.
+/–1
+/–1
150
300
410
27
10
12
10
Max
1.9
1.9
3.6
2.7
1.9
1.6
3.6
Units
Units
Units
mA
μA
μA
μA
pF
pF
pF
μA
μA
°C
°C
V
V
V
V
V
V
V
V
V
V
V
V
V
3

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