XC2C256-7VQG100C Xilinx Inc, XC2C256-7VQG100C Datasheet - Page 14

• Manufacturer Part Number: XC2C256-7VQG100C
• Description: IC CR-II CPLD 256MCELL 100-VQFP
• Manufacturer: Xilinx Inc
• Series: CoolRunner IIr

Specifications of XC2C256-7VQG100C

• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 6.7ns
• Voltage Supply - Internal: 1.7 V ~ 1.9 V
• Number Of Logic Elements/blocks: 16
• Number Of Macrocells: 256
• Number Of Gates: 6000
• Number Of I /o: 80
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Features: Programmable
• Voltage: 1.8V
• Memory Type: CMOS
• No. Of Macrocells: 256
• No. Of I/o's: 80
• Propagation Delay: 5.7ns
• Global Clock Setup Time: 3.3ns
• Frequency: 152MHz
• Supply Voltage Range: 1.7V To 1.9V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 122-1573 - KIT STARTER COOLRUNNER-II LP/LC122-1512 - KIT DESIGN CPLD W/BATT HOLDER
• Number Of Logic Elements/cells: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1402

XC2C256 CoolRunner-II CPLD
Pin Descriptions (Continued)
14
Function
Block
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
Macro-
cell
10
12
13
14
15
16
10
12
13
14
15
16
11
11
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
VQ100 CP132 TQ144 PQ208 FT256
53
54
55
56
52
50
49
46
44
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
M12
M13
M14
N13
N14
P14
P12
M11
P10
L12
L13
N11
P11
P9
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
75
76
77
78
79
80
81
82
74
71
70
69
68
66
64
61
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
107
108
109
106
103
102
101
100
110
111
112
113
114
115
116
117
99
97
95
91
-
-
-
-
-
-
-
-
-
-
-
-
M15
M13
M14
R15
N14
R16
N15
P16
N16
P15
P14
P13
R13
N13
R14
R12
N11
M11
N10
T16
L14
T15
-
-
-
-
-
-
-
-
-
-
www.xilinx.com
Bank
I/O
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
-
-
-
-
-
-
-
-
-
-
Pin Descriptions (Continued)
Notes:
1.
2.
Function
Block
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
GTS = global output enable, GSR = global reset/set, GCK =
global clock, CDRST = clock divide reset, DGE = DataGATE
enable.
GTS, GSR and GCK pins can be used for general purpose I/O.
Macro-
cell
10
12
13
14
15
16
10
12
13
14
15
16
11
11
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
VQ100 CP132 TQ144 PQ208 FT256
58
59
41
40
60
61
63
64
43
42
39
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
K13
H13
H12
L14
K14
J12
J13
M8
M7
N8
N7
P8
P6
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
DS094 (v3.2) March 8, 2007
83
85
86
87
88
91
92
60
59
58
57
56
54
53
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Product Specification
120
121
122
123
125
126
127
128
131
118
119
90
89
88
87
86
85
84
83
82
80
78
77
-
-
-
-
-
-
-
-
-
M12
M16
K14
K15
K16
P10
R10
L15
L13
L16
L12
T10
J14
J15
J13
M8
R9
N9
P8
R8
N8
T8
T7
T6
-
-
-
-
-
-
-
-
Bank
I/O
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
-
-
-
-
-
-
-
-
R