EPM2210F256I5 Altera, EPM2210F256I5 Datasheet - Page 37

• Manufacturer Part Number: EPM2210F256I5
• Description: IC MAX II CPLD 2210 LE 256-FBGA
• Manufacturer: Altera
• Series: MAX® IIr

Specifications of EPM2210F256I5

• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 7.0ns
• Voltage Supply - Internal: 2.5V, 3.3V
• Number Of Logic Elements/blocks: 2210
• Number Of Macrocells: 1700
• Number Of I /o: 204
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 256-FBGA
• Voltage: 2.5V, 3.3V
• Memory Type: FLASH
• Number Of Logic Elements/cells: 2210
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Other names: 544-2267

Chapter 2: MAX II Architecture
I/O Structure
Schmitt Trigger
Output Enable Signals
Programmable Drive Strength
© October 2008 Altera Corporation
1
Table 2–5. MAX II Devices and Speed Grades that Support 3.3-V PCI Electrical Specifications and
Meet PCI Timing
The input buffer for each MAX II device I/O pin has an optional Schmitt trigger
setting for the 3.3-V and 2.5-V standards. The Schmitt trigger allows input buffers to
respond to slow input edge rates with a fast output edge rate. Most importantly,
Schmitt triggers provide hysteresis on the input buffer, preventing slow-rising noisy
input signals from ringing or oscillating on the input signal driven into the logic array.
This provides system noise tolerance on MAX II inputs, but adds a small, nominal
input delay.
The JTAG input pins (TMS, TCK, and TDI) have Schmitt trigger buffers that are always
enabled.
The TCK input is susceptible to high pulse glitches when the input signal fall time is
greater than 200 ns for all I/O standards.
Each MAX II IOE output buffer supports output enable signals for tri-state control.
The output enable signal can originate from the GCLK[3..0] global signals or from
the MultiTrack interconnect. The MultiTrack interconnect routes output enable signals
and allows for a unique output enable for each output or bidirectional pin.
MAX II devices also provide a chip-wide output enable pin (DEV_OE) to control the
output enable for every output pin in the design. An option set before compilation in
the Quartus II software controls this pin. This chip-wide output enable uses its own
routing resources and does not use any of the four global resources. If this option is
turned on, all outputs on the chip operate normally when DEV_OE is asserted. When
the pin is deasserted, all outputs are tri-stated. If this option is turned off, the DEV_OE
pin is disabled when the device operates in user mode and is available as a user I/O
pin.
The output buffer for each MAX II device I/O pin has two levels of programmable
drive strength control for each of the LVTTL and LVCMOS I/O standards.
Programmable drive strength provides system noise reduction control for high
performance I/O designs. Although a separate slew-rate control feature exists, using
the lower drive strength setting provides signal slew-rate control to reduce system
noise and signal overshoot without the large delay adder associated with the
slew-rate control feature.
with drive strength control. The Quartus II software uses the maximum current
strength as the default setting. The PCI I/O standard is always set at 20 mA with no
alternate setting.
EPM1270
EPM2210
Device
Table 2–6
All Speed Grades
All Speed Grades
33-MHz PCI
shows the possible settings for the I/O standards
–3 Speed Grade
–3 Speed Grade
66-MHz PCI
MAX II Device Handbook
2–29