EPM2210F256I5 Altera, EPM2210F256I5 Datasheet - Page 46

• Manufacturer Part Number: EPM2210F256I5
• Description: IC MAX II CPLD 2210 LE 256-FBGA
• Manufacturer: Altera
• Series: MAX® IIr

Specifications of EPM2210F256I5

• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 7.0ns
• Voltage Supply - Internal: 2.5V, 3.3V
• Number Of Logic Elements/blocks: 2210
• Number Of Macrocells: 1700
• Number Of I /o: 204
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 256-FBGA
• Voltage: 2.5V, 3.3V
• Memory Type: FLASH
• Number Of Logic Elements/cells: 2210
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Other names: 544-2267

3–4
Figure 3–1. MAX II Parallel Flash Loader
Notes to
(1) This block is implemented in LEs.
(2) This function is supported in the Quartus II software.
In System Programmability
MAX II Device Handbook
Figure
3–1:
Memory Device
Flash
DQ[7..0]
A[20..0]
MAX II devices can be programmed in-system via the industry standard 4-pin IEEE
Std. 1149.1 (JTAG) interface. In-system programmability (ISP) offers quick, efficient
iterations during design development and debugging cycles. The logic, circuitry, and
interconnects in the MAX II architecture are configured with flash-based SRAM
configuration elements. These SRAM elements require configuration data to be
loaded each time the device is powered. The process of loading the SRAM data is
called configuration. The on-chip configuration flash memory (CFM) block stores the
SRAM element’s configuration data. The CFM block stores the design’s configuration
pattern in a reprogrammable flash array. During ISP, the MAX II JTAG and ISP
circuitry programs the design pattern into the CFM block’s non-volatile flash array.
The MAX II JTAG and ISP controller internally generate the high programming
voltages required to program the CFM cells, allowing in-system programming with
any of the recommended operating external voltage supplies (that is, 3.3 V/2.5 V or
1.8 V for the MAX IIG and MAX IIZ devices). ISP can be performed anytime after
V
configuration power-up time. By default, during in-system programming, the I/O
pins are tri-stated and weakly pulled-up to V
system programming clamp and real-time ISP feature allow user control of I/O state
or behavior during ISP.
For more information, refer to
“Real-Time ISP” on page
These devices also offer an ISP_DONE bit that provides safe operation when in-
system programming is interrupted. This ISP_DONE bit, which is the last bit
programmed, prevents all I/O pins from driving until the bit is programmed.
RY/BY
CCINT
WE
OE
CE
TMS
TDO
and all V
TCK
TDI
CCIO
RUNIDLE_U
UPDATE_U
banks have been fully powered and the device has completed the
CLKDR_U
USER1_U
SHIFT_U
TDO_U
TMS_U
TCK_U
TDI_U
3–7.
“In-System Programming Clamp” on page 3–6
MAX II Device
Configuration
DQ[7..0]
A[20..0]
OE
WE
CE
RY/BY
Flash Loader
Parallel
(1), (2)
Logic
CCIO
to eliminate board conflicts. The in-
Chapter 3: JTAG and In-System Programmability
© October 2008 Altera Corporation
CONF_DONE
nSTATUS
nCE
DATA0
nCONFIG
DCLK
Altera FPGA
In System Programmability
and