EPM7064AETC44-4N Altera, EPM7064AETC44-4N Datasheet - Page 52

IC MAX 7000 CPLD 64 44-TQFP

EPM7064AETC44-4N

Manufacturer Part Number
EPM7064AETC44-4N
Description
IC MAX 7000 CPLD 64 44-TQFP
Manufacturer
Altera
Series
MAX® 7000Ar
Datasheet

Specifications of EPM7064AETC44-4N

Programmable Type
In System Programmable
Delay Time Tpd(1) Max
4.5ns
Voltage Supply - Internal
3 V ~ 3.6 V
Number Of Logic Elements/blocks
4
Number Of Macrocells
64
Number Of Gates
1250
Number Of I /o
36
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
44-TQFP, 44-VQFP
Voltage
2.5V, 3.3V
Memory Type
CMOS
Number Of Logic Elements/cells
4
Family Name
MAX 7000A
# Macrocells
64
Number Of Usable Gates
1250
Frequency (max)
250MHz
Propagation Delay Time
4.5ns
Number Of Logic Blocks/elements
4
# I/os (max)
36
Operating Supply Voltage (typ)
3.3V
In System Programmable
Yes
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
44
Package Type
TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2582
EPM7064AETC44-4N

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EPM7064AETC44-4N
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EPM7064AETC44-4N
Manufacturer:
ALTERA
Quantity:
4 000
Part Number:
EPM7064AETC44-4N
Manufacturer:
ALTERA
0
MAX 7000A Programmable Logic Device Data Sheet
52
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
f
t
f
Symbol
PD1
PD2
SU
H
FSU
FH
CO1
CH
CL
ASU
AH
ACO1
ACH
ACL
CPPW
CNT
CNT
ACNT
ACNT
Table 29. EPM7256A External Timing Parameters
Input to non-registered
output
I/O input to non-
registered output
Global clock setup time
Global clock hold time
Global clock setup time
of fast input
Global clock hold time of
fast input
Global clock to output
delay
Global clock high time
Global clock low time
Array clock setup time
Array clock hold time
Array clock to output
delay
Array clock high time
Array clock low time
Minimum pulse width for
clear and preset
Minimum global clock
period
Maximum internal global
clock frequency
Minimum array clock
period
Maximum internal array
clock frequency
Parameter
C1 = 35 pF
(2)
C1 = 35 pF
(2)
(2)
(2)
C1 = 35 pF
(2)
(2)
C1 = 35 pF
(2)
(3)
(2)
(2),
(2)
(2),
Conditions
(4)
(4)
156.3
156.3
Min
3.0
3.7
0.0
2.5
0.0
1.0
3.0
3.0
0.8
1.9
1.0
3.0
3.0
-6
Max
6.0
6.0
3.3
6.2
6.4
6.4
Note (1)
125.0
125.0
Min
3.0
4.6
0.0
3.0
0.0
1.0
3.0
3.0
1.0
2.7
1.0
3.0
3.0
-7
Speed Grade
Max
7.5
7.5
4.2
7.8
8.0
8.0
93.5
93.5
Min
4.0
6.2
0.0
3.0
0.0
1.0
4.0
4.0
1.4
4.0
1.0
4.0
4.0
-10
Max
10.0
10.0
10.3
10.7
10.7
5.5
Altera Corporation
78.1
78.1
Min
7.4
0.0
3.0
0.0
1.0
4.0
4.0
1.6
5.1
1.0
4.0
4.0
4.0
-12
Max
12.0
12.0
12.4
12.8
12.8
6.6
MHz
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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