CY7C372I-100JC Cypress Semiconductor Corp, CY7C372I-100JC Datasheet - Page 2

• Manufacturer Part Number: CY7C372I-100JC
• Description: IC CPLD 64 MACROCELL 44-PLCC
• Manufacturer: Cypress Semiconductor Corp
• Series: Ultralogic™r

Specifications of CY7C372I-100JC

• Memory Type: FLASH
• Programmable Type: In-System Reprogrammable™ (ISR™) Flash
• Delay Time Tpd(1) Max: 12.0ns
• Voltage Supply - Internal: 4.75 V ~ 5.25 V
• Number Of Logic Elements/blocks: 4
• Number Of Macrocells: 64
• Number Of I /o: 32
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 44-PLCC
• Voltage: 3.3V/5V
• Family Name: FLASH370i
• # Macrocells: 64
• Number Of Usable Gates: 1600
• Propagation Delay Time: 12ns
• Number Of Logic Blocks/elements: 4
• # I/os (max): 32
• Operating Supply Voltage (typ): 5V
• In System Programmable: Yes
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Number Of Logic Elements/cells: -
• Lead Free Status / RoHS Status: Not Compliant, Contains lead / RoHS non-compliant
• Other names: 428-1268

Pin Configurations
Functional Description
Like all members of the F
in I/O resources. Every two macrocells in the device feature an
associated I/O pin, resulting in 32 I/O pins on the CY7C372i.
In addition, there are three dedicated inputs and two in-
put/clock pins.
Finally, the CY7C372i features a very simple timing model.
Unlike other high-density CPLD architectures, there are no
hidden speed delays such as fanout effects, interconnect de-
lays, or expander delays. Regardless of the number of re-
sources used. or the type of application, the timing parameters
on the CY7C372i remain the same.
Logic Block
The number of logic blocks distinguishes the members of the
F
Each logic block is constructed of a product term array, a prod-
uct term allocator, and 16 macrocells.
Product Term Array
The product term array in the F
36 inputs from the PIM and outputs 86 product terms to the
product term allocator. The 36 inputs from the PIM are avail-
able in both positive and negative polarity, making the overall
array size 72 x 86. This large array in each logic block allows
for very complex functions to be implemented in a single pass
through the device.
Product Term Allocator
The product term allocator is a dynamic, configurable resource
that shifts product terms to macrocells that require them. Any
number of product terms between 0 and 16 inclusive can be
assigned to any of the logic block macrocells (this is called
product term steering). Furthermore, product terms can be
shared among multiple macrocells. This means that product
terms that are common to more than one output can be imple-
mented in a single product term. Product term steering and
product term sharing help to increase the effective density of
Document #: 38-03033 Rev. **
LASH
370i family. The CY7C372i includes four logic blocks.
I/O
CLK
5
/SCLK
ISR
I/O
I/O
GND
I/O
I/O
I/O
I/O
0
/I
EN
10
11
I
6
1
8
7
0
9
7
8
9
10
11
12
13
14
15
16
17
18
6 5
19 20
LASH
4
21
3
370i family, the CY7C372i is rich
TopView
22
(continued)
PLCC
2
LASH
23 24
1 44
25
370i logic block includes
43 42
26
27
41
28
40
39
38
37
36
35
34
33
32
31
30
29
I/O
I/O
I/O
I/O
CLK
GND
I
I
I/O
I/O
I/O
3
2
7c372i-2
27
26
25
24
23
22
21
1
/SDI
/I
4
the F
dled by software and is invisible to the user.
I/O Macrocell
Half of the macrocells on the CY7C372i have separate I/O pins
associated with them. In other words, each I/O pin is shared
by two macrocells. The input to the macrocell is the sum of
between 0 and 16 product terms from the product term alloca-
tor. The macrocell includes a register that can be optionally
bypassed. It also has polarity control, and two global clocks to
trigger the register. The I/O macrocell also features a separate
feedback path to the PIM so that the register can be buried if
the I/O pin is used as an input.
Buried Macrocell
The buried macrocell is very similar to the I/O macrocell.
Again, it includes a register that can be configured as combi-
natorial, as a D flip-flop, a T flip-flop, or a latch. The clock for
this register has the same options as described for the I/O
macrocell. One difference on the buried macrocell is the addi-
tion of input register capability. The user can program the bur-
ied macrocell to act as an input register (D-type or latch)
whose input comes from the I/O pin associated with the neigh-
boring macrocell. The output of all buried macrocells is sent
directly to the PIM regardless of its configuration.
Programmable Interconnect Matrix
The Programmable Interconnect Matrix (PIM) connects the
four logic blocks on the CY7C372i to the inputs and to each
other. All inputs (including feedbacks) travel through the PIM.
There is no speed penalty incurred by signals traversing the
PIM.
Programming
For an overview of ISR programming, refer to the F
Family data sheet and for ISR cable and software specifica-
tions, refer to ISR data sheets. For a detailed description of
ISR capabilities, refer to the Cypress application note, “An In-
troduction to In System Reprogramming with F
LASH
I/O
CLK
5
/SCLK
ISR
370 PLDs. Note that product term allocation is han-
I/O
I/O
GND
I/O
I/O
I/O
I/O
0
EN
/I
10
11
I
6
1
8
7
0
9
7
8
9
10
11
12
13
14
15
16
17
18 19 20 21 22 23 24 25 26 27 28
6 5 4 3 2
TopView
CLCC
1
44 43 42 41 40
39
38
37
36
35
34
33
32
31
30
29
CY7C372i
7c372i–4
I/O
I/O
I/O
I/O
CLK
GND
I
I
I/O
I/O
I/O
LASH
3
2
Page 2 of 12
27
26
25
24
23
22
21
1
/SDI
/I
4
370i.”
LASH
370i