CY39100V208B-125NTC Cypress Semiconductor Corp, CY39100V208B-125NTC Datasheet - Page 3
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CY39100V208B-125NTC
Manufacturer Part Number
CY39100V208B-125NTC
Description
IC CPLD 100K GATE 208BQFP
Manufacturer
Cypress Semiconductor Corp
Series
Delta 39K™ ISR™r
Datasheet
1.CY39030V208-125NTXC.pdf
(91 pages)
Specifications of CY39100V208B-125NTC
Programmable Type
In-System Reprogrammable™ (ISR™) Flash
Delay Time Tpd(1) Max
10.0ns
Voltage Supply - Internal
2.5V, 3.3V
Number Of Macrocells
1536
Number Of Gates
144000
Number Of I /o
136
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
208-QFP
Voltage
1.8V, 2.5V, 3.3V
Memory Type
FLASH
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Number Of Logic Elements/cells
-
Other names
428-1294
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CY39100V208B-125NTC
Manufacturer:
CY
Quantity:
253
Company:
Part Number:
CY39100V208B-125NTC
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
General Description
The Delta39K™ family, based on a 0.18- m, six-layer metal
CMOS logic process, offers a wide range of high-density
solutions at unparalleled system performance. The Delta39K
family is designed to combine the high speed, predictable
timing, and ease of use of CPLDs with the high densities and
low power of FPGAs. With devices ranging from 30,000 to
200,000 usable gates, the family features devices ten times
the size of previously available CPLDs. Even at these large
Document #: 38-03039 Rev. *D
GCLK[3:0]
GCLK[3:0]
GCLK[3:0]
GCLK[3:0]
PLL and Clock MUX
Cluster
Cluster
LB 0
LB 1
LB 2
LB 3
LB 0
LB 1
LB 2
LB 3
Cluster
RAM
RAM
LB 0
LB 1
LB 2
LB 3
RAM
Figure 1. Delta39K100 Block Diagram (Three Rows × Four Columns) with I/O Bank Structure
PIM
PIM
PIM
Cluster
Cluster
LB 7
LB 6
LB 5
LB 4
LB 7
LB 6
LB 5
LB 4
Cluster
RAM
RAM
LB 7
LB 6
LB 5
LB 4
4
RAM
4
4
4
4
Channel
Channel
Channel
RAM
RAM
RAM
GCTL[3:0]
PRELIMINARY
Cluster
Cluster
LB 0
LB 1
LB 2
LB 3
LB 0
LB 1
LB 2
LB 3
Cluster
RAM
RAM
LB 0
LB 1
LB 2
LB 3
RAM
I/O Bank 2
I/O Bank 7
PIM
PIM
PIM
Cluster
Cluster
LB 7
LB 6
LB 5
LB 4
LB 7
LB 6
LB 5
LB 4
Cluster
RAM
RAM
LB 7
LB 6
LB 5
LB 4
RAM
4
4
4
Channel
Channel
Channel
RAM
RAM
RAM
Cluster
Cluster
LB 0
LB 1
LB 2
LB 3
LB 0
LB 1
LB 2
LB 3
Cluster
RAM
RAM
LB 0
LB 1
LB 2
LB 3
RAM
densities, the Delta39K family is fast enough to implement a
fully synthesizable 64-bit, 66-MHz PCI core.
The architecture is based on Logic Block Clusters (LBC) that
are connected by Horizontal and Vertical (H and V) routing
channels. Each LBC features eight individual Logic Blocks
(LB) and two cluster memory blocks. Adjacent to each LBC is
a channel memory block, which can be accessed directly from
the I/O pins. Both types of memory blocks are highly config-
urable and can be cascaded in width and depth. See Figure 1
for a block diagram of the Delta39K architecture.
PIM
PIM
PIM
Cluster
Cluster
LB 7
LB 6
LB 5
LB 4
LB 7
LB 6
LB 5
LB 4
Cluster
RAM
RAM
LB 7
LB 6
LB 5
LB 4
RAM
4
4
4
Channel
Channel
Channel
RAM
RAM
RAM
Cluster
Cluster
LB 0
LB 1
LB 2
LB 3
LB 0
LB 1
LB 2
LB 3
Cluster
RAM
RAM
LB 0
LB 1
LB 2
LB 3
RAM
Delta39K™ ISR™
I/O Bank 3
I/O Bank 6
PIM
PIM
PIM
Cluster
Cluster
LB 7
LB 6
LB 5
LB 4
LB 7
LB 6
LB 5
LB 4
Cluster
RAM
RAM
LB 7
LB 6
LB 5
LB 4
RAM
CPLD Family
4
4
4
Channel
Channel
Channel
RAM
RAM
RAM
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