CY39100V388B-125MGC Cypress Semiconductor Corp, CY39100V388B-125MGC Datasheet - Page 20
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CY39100V388B-125MGC
Manufacturer Part Number
CY39100V388B-125MGC
Description
IC CPLD 100K GATE 388-BGA
Manufacturer
Cypress Semiconductor Corp
Series
Delta 39K™ ISR™r
Datasheet
1.CY39030V208-125NTXC.pdf
(91 pages)
Specifications of CY39100V388B-125MGC
Programmable Type
In-System Reprogrammable™ (ISR™) Flash
Delay Time Tpd(1) Max
10.0ns
Voltage Supply - Internal
2.5V, 3.3V
Number Of Macrocells
1536
Number Of Gates
144000
Number Of I /o
294
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
388-BGA
Voltage
1.8V, 2.5V, 3.3V
Memory Type
FLASH
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Number Of Logic Elements/cells
-
Other names
428-1295
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CY39100V388B-125MGC
Manufacturer:
CY
Quantity:
146
Company:
Part Number:
CY39100V388B-125MGC
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Cluster Memory Timing Parameter Descriptions
Document #: 38-03039 Rev. *D
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Synchronous Mode Parameters
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CLMAA
CLMPWE
CLMSA
CLMHA
CLMSD
CLMHD
CLMCYC1
CLMCYC2
CLMS
CLMH
CLMDV1
CLMDV2
CLMMACS1
CLMMACS2
MACCLMS1
MACCLMS2
CLMCLAA
Asynchronous Mode Parameters
Internal Parameters
Parameter
Cluster memory access time. Delay from address change to Read data out
Write Enable pulse width
Address set-up to the beginning of Write Enable with both signals from the same I/O block
Address hold after the end of Write Enable with both signals from the same I/O block
Data set-up to the end of Write Enable
Data hold after the end of Write Enable
Clock cycle time for flow through Read and Write operations (from macrocell register through cluster
memory back to a macrocell register in the same cluster)
Clock cycle time for pipelined Read and Write operations (from cluster memory input register through the
memory to cluster memory output register)
Address, data, and WE set-up time of pin inputs, relative to a global clock
Address, data, and WE hold time of pin inputs, relative to a global clock
Global clock to data valid on output pins for flow through data
Global clock to data valid on output pins for pipelined data
Cluster memory input clock to macrocell clock in the same cluster
Cluster memory output clock to macrocell clock in the same cluster
Macrocell clock to cluster memory input clock in the same cluster
Macrocell clock to cluster memory output clock in the same cluster
Asynchronous cluster memory access time from input of cluster memory to output of cluster memory
PRELIMINARY
Over the Operating Range
Description
Delta39K™ ISR™
CPLD Family
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