ADSP-BF527KBCZ-6C2 Analog Devices Inc, ADSP-BF527KBCZ-6C2 Datasheet - Page 20

• Manufacturer Part Number: ADSP-BF527KBCZ-6C2
• Description: IC DSP 16BIT 600MHZ 289CSPBGA
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r
• Type: Fixed Pointr

Specifications of ADSP-BF527KBCZ-6C2

• Package / Case: 289-CSPBGA
• Interface: DMA, Ethernet, I²C, PPI, SPI, SPORT, UART, USB
• Clock Rate: 600MHz
• Non-volatile Memory: ROM (32 kB)
• On-chip Ram: 132kB
• Voltage - I/o: 1.8V, 2.5V, 3.3V
• Voltage - Core: 1.10V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Svhc: No SVHC (18-Jun-2010)
• Cache On Chip L1/l2 Memory: 48KB
• Core Frequency Typ: 600MHz
• Dsp Type: Core
• External Supported Memory: SDRAM, SRAM, FLASH, ROM
• Interface Type: SPI, Parallel, 2 Wire
• Rohs Compliant: Yes
• Mmac: 1200
• No. Of Pins: 289
• Package: 289CSP-BGA
• Maximum Speed: 600 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: ADZS-BF527-MPSKIT - BOARD EVAL MEDIA PLAYER BF527ADZS-BF527-EZLITE - BOARD EVAL ADSP-BF527
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Table 11. Register 7 Digital Audio I/F
Table 12. Register 8 Sampling Rate
Table 13. Register 9 Active
Table 14. Register 10 Software Reset
Bit Name
BCLKINV
MS
LRSWAP
LRP
WL [1:0]
FORMAT [1:0] B[1:0] Digital audio input format control
Bit Name
CLKODIV2
CLKDIV2
SR [3:0]
BOSR
USB
Bit Name
ACTIVE
Bit Name
RESET [8:0] B[8:0] Write all 0s to this register to set all registers to their default settings.
ADSP-BF522C/ADSP-BF523C/ADSP-BF524C/ADSP-BF525C/ADSP-BF526C/ADSP-BF527C
Bit
Bits
B7
B6
B5
B4
B[3:2] Data-word length control
Bits
B7
B6
B[5:2]
B1
B0
Bit
B0
Description
Other data written to this register has no effect.
Description
CODEC_BCLK inversion control
Master mode enable
Swap DAC data control
Polarity control for clocks in right-justified,
left-justified, and I
Description
Digital core activation control
Description
CODEC_CLKOUT divider select
Codec clock divide select
Clock setting condition
Base oversampling rate
USB mode select
2
S modes
Rev. A | Page 20 of 36 | March 2010
Settings
0 = CODEC_CLKOUT is codec clock (default)
1 = CODEC_CLKOUT is codec clock divided by 2
0 = codec clock is CODEC_MCLK (default)
1= codec clock is CODEC_MCLK divided by 2
See
USB mode:
0 = support for 250 × f
1 = support for 272 × f
Normal mode:
0 = support for 256 × f
1 = support for 384 × f
0 = normal mode enable (default)
1 = USB mode enable
Settings
0 = CODEC_BCLK not inverted (default)
1 = CODEC_BCLK inverted
0 = enable slave mode (default)
1 = enable master mode
0 = output left- and right-channel data as normal (default)
1 = swap left- and right-channel DAC data in audio interface
0 = normal DACLRC and ADCLRC (default),
or processor Submode 1
1 = invert DACLRC and ADCLRC polarity, or processor Submode 2
00 = 16 bits
01 = 20 bits
10 = 24 bits (default)
11 = 32 bits
00 = right justified
01 = left justified
10 = I
11 = processor mode
Table 1 on Page 9
2
S mode (default)
Settings
0 = disable digital core (default)
1 = activate digital core
and
S
S
S
S
based clock (default)
based clock
based clock (default)
based clock
Table 2 on Page 10
Settings
0 = reset (default)