ADSP-BF527KBCZ-6C2 Analog Devices Inc, ADSP-BF527KBCZ-6C2 Datasheet - Page 25

• Manufacturer Part Number: ADSP-BF527KBCZ-6C2
• Description: IC DSP 16BIT 600MHZ 289CSPBGA
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r
• Type: Fixed Pointr

Specifications of ADSP-BF527KBCZ-6C2

• Package / Case: 289-CSPBGA
• Interface: DMA, Ethernet, I²C, PPI, SPI, SPORT, UART, USB
• Clock Rate: 600MHz
• Non-volatile Memory: ROM (32 kB)
• On-chip Ram: 132kB
• Voltage - I/o: 1.8V, 2.5V, 3.3V
• Voltage - Core: 1.10V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Svhc: No SVHC (18-Jun-2010)
• Cache On Chip L1/l2 Memory: 48KB
• Core Frequency Typ: 600MHz
• Dsp Type: Core
• External Supported Memory: SDRAM, SRAM, FLASH, ROM
• Interface Type: SPI, Parallel, 2 Wire
• Rohs Compliant: Yes
• Mmac: 1200
• No. Of Pins: 289
• Package: 289CSP-BGA
• Maximum Speed: 600 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: ADZS-BF527-MPSKIT - BOARD EVAL MEDIA PLAYER BF527ADZS-BF527-EZLITE - BOARD EVAL ADSP-BF527
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

TIMING SPECIFICATIONS
TWI Timing
Table 17. TWI Timing
1
Parameter
t
t
t
t
f
t
t
t
t
t
AVDD, HPVDD, V
SCS
SCH
PH
PL
SCL
DS
DH
RT
FT
HCS
ADSP-BF522C/ADSP-BF523C/ADSP-BF524C/ADSP-BF525C/ADSP-BF526C/ADSP-BF527C
CSDA
CSCL
Start condition setup time
Start condition hold time
CSCL pulse width high
CSCL pulse width low
CSCL frequency
Data setup time
Data hold time
CSDA and CSCL rise time
CSDA and CSCL fall time
Stop condition setup time
DDEXT
= 3.3 V, AGND = 0 V, T
t
SCH
A
= +25°C, Slave Mode, f
t
RT
t
PL
Rev. A | Page 25 of 36 | March 2010
Figure 18. TWI Timing
S
= 48 kHz, XTI/CODEC_MCLK = 256 × f
t
DS
t
DH
t
PH
t
FT
S
t
unless otherwise stated.
SCS
Test Conditions
t
HCS
1
Min Max Unit
600
600
600
1.3
0
100
600
526 kHz
900 ns
300 ns
300 ns
ns
ns
ns
μs
ns
ns