ADSP-2173BST-80 Analog Devices Inc, ADSP-2173BST-80 Datasheet - Page 6

• Manufacturer Part Number: ADSP-2173BST-80
• Description: IC DSP CONTROLLER 16BIT 128TQFP
• Manufacturer: Analog Devices Inc
• Series: ADSP-21xxr
• Type: Fixed Pointr

Specifications of ADSP-2173BST-80

• Rohs Status: RoHS non-compliant
• Interface: Host Interface, Serial Port
• Clock Rate: 20MHz
• Non-volatile Memory: External
• On-chip Ram: 10kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-TQFP, 128-VQFP
• Device Core Size: 16b
• Architecture: Enhanced Harvard
• Format: Fixed Point
• Clock Freq (max): 20MHz
• Mips: 20
• Device Input Clock Speed: 20MHz
• Ram Size: 10KB
• Program Memory Size: 24KB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 128
• Package Type: TQFP
• Lead Free Status / Rohs Status: Not Compliant

ADSP-2171/ADSP-2172/ADSP-2173
LOW POWER OPERATION
The ADSP-217x has three low power modes that significantly
reduce the power dissipation when the device operates under
standby conditions. These modes are:
The CLKOUT pin may also be disabled to reduce external
power dissipation. The CLKOUT pin is controlled by Bit 14 of
SPORT0 Autobuffer Control Register, DM[0x3FF3].
Powerdown
The ADSP-217x processor has a low power feature that lets the
processor enter a very low power dormant state through hard-
ware or software control. Here is a brief list of powerdown fea-
tures. Refer to the ADSP-2100 Family User’s Manual, Chapter 9
“System Interface” for detailed information about the
powerdown feature.
Idle
When the ADSP-217x is in the Idle Mode, the processor waits
indefinitely in a low power state until an interrupt occurs. When
an unmasked interrupt occurs, it is serviced; execution then
continues with the instruction following the IDLE instruction.
Slow Idle
The IDLE instruction is enhanced on the ADSP-217x to let the
processor’s internal clock signal be slowed during IDLE, further
reducing power consumption. The reduced clock frequency, a
Powerdown
Idle
Slow Idle
Powerdown mode holds the processor in CMOS standby with
Quick recovery from powerdown. The processor begins ex-
Support for an externally generated TTL or CMOS processor
Support for crystal operation includes disabling the oscillator
Powerdown is initiated by either the powerdown pin (PWD)
Interrupt support allows an unlimited number of instructions
Context clear/save control allows the processor to continue
The RESET pin also can be used to terminate powerdown,
Powerdown acknowledge pin indicates when the processor has
a maximum current of less than 100 A in some modes.
ecuting instructions in as few as 100 CLKIN cycles.
clock. The external clock can continue running during
powerdown without affecting the lowest power rating and 100
CLKIN cycle recovery.
to save power (the processor automatically waits 4096 CLKIN
cycles for the crystal oscillator to start and stabilize), and let-
ting the oscillator run to allow 100 CLKIN cycle startup.
or the software powerdown force bit.
to be executed before optionally powering down. The
powerdown interrupt also can be used as a non-maskable,
edge sensitive interrupt.
where it left off or start with a clean context when leaving the
powerdown state.
and the host software reset feature can be used to terminate
powerdown under certain conditions.
entered powerdown.
–6–
programmable fraction of the normal clock rate, is specified by a
selectable divisor given in the IDLE instruction. The format of
the instruction is
IDLE (n);
where n = 16, 32, 64, or 128. This instruction keeps the proces-
sor fully functional, but operating at the slower clock rate. While
it is in this state, the processor’s other internal clock signals,
such as SCLK, CLKOUT, and timer clock, are reduced by the
same ratio. The default form of the instruction, when no clock
divisor is given, is the standard IDLE instruction.
When the IDLE (n) instruction is used, it effectively slows down
the processor’s internal clock and thus its response time to in-
coming interrupts––the 1-cycle response time of the standard
idle state is increased by n, the clock divisor. When an enabled
interrupt is received, the ADSP-217x will remain in the idle
state for up to a maximum of n processor cycles (n = 16, 32, 64,
or 128) before resuming normal operation.
When the IDLE (n) instruction is used in systems that have an
externally generated serial clock (SCLK), the serial clock rate
may be faster than the processor’s reduced internal clock rate.
Under these conditions, interrupts must not be generated at a
faster rate than can be serviced, due to the additional time the
processor takes to come out of the idle state (a maximum of n
processor cycles).
SYSTEM INTERFACE
Figure 3 shows a basic system configuration with the ADSP-
217x, two serial devices, a host processor, a boot EPROM, and
optional external program and data memories. Up to 14K words
of data memory and 16K words of program memory can be sup-
ported. Programmable wait state generation allows the processor
to interface easily to slow memories. The ADSP-217x also pro-
vides one external interrupt and two serial ports or three exter-
nal interrupts and one serial port.
Clock Signals
The ADSP-217x can be clocked by either a crystal or by a TTL-
compatible clock signal.
The CLKIN input cannot be halted, changed during operation,
or operated below the specified frequency during normal opera-
tion. The only exception is while the processor is in the Power-
down State. For additional information, refer to Chapter 9,
ADSP-2100 Family User’s Manual for detailed information on
this powerdown feature.
If an external clock is used, it should be a TTL-compatible sig-
nal running at half the instruction rate. The signal is connected
to the processor’s CLKIN input. When an external clock is
used, the XTAL input must be left unconnected.
The ADSP-217x uses an input clock with a frequency equal to
half the instruction rate; a 16.67 MHz input clock yields a 30 ns
processor cycle (which is equivalent to 33 MHz). Normally, in-
structions are executed in a single processor cycle. All device
timing is relative to the internal instruction clock rate, which is
indicated by the CLKOUT signal when enabled.
REV. A