ADSP-2188MKST-300 Analog Devices Inc, ADSP-2188MKST-300 Datasheet - Page 14

• Manufacturer Part Number: ADSP-2188MKST-300
• Description: IC DSP CONTROLLER 16BIT 100LQFP
• Manufacturer: Analog Devices Inc
• Series: ADSP-21xxr
• Type: Fixed Pointr

Specifications of ADSP-2188MKST-300

• Rohs Status: RoHS non-compliant
• Interface: Host Interface, Serial Port
• Clock Rate: 75MHz
• Non-volatile Memory: External
• On-chip Ram: 256kB
• Voltage - I/o: 3.30V
• Voltage - Core: 2.50V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Device Core Size: 16b
• Architecture: Enhanced Harvard
• Format: Fixed Point
• Clock Freq (max): 75MHz
• Mips: 75
• Device Input Clock Speed: 75MHz
• Ram Size: 256KB
• Operating Supply Voltage (typ): 2.75/3.3V
• Operating Supply Voltage (min): 2.61V
• Operating Supply Voltage (max): 2.89/3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: LQFP
• Lead Free Status / Rohs Status: Not Compliant

I/O Space (Full Memory Mode)
The ADSP-2188M supports an additional external memory
space called I/O space. This space is designed to support simple
connections to peripherals (such as data converters and external
registers) or to bus interface ASIC data registers. I/O space sup-
ports 2048 locations of 16-bit wide data. The lower eleven bits
of the external address bus are used; the upper three bits are
undefined. Two instructions were added to the core ADSP-2100
Family instruction set to read from and write to I/O memory
space. The I/O space also has four dedicated three-bit wait state
registers, IOWAIT0–3, which in combination with the wait state
mode bit, specify up to 15 wait states to be automatically gener-
ated for each of four regions. The wait states act on address
ranges as shown in Table V.
Address Range
0x000–0x1FF
0x200–0x3FF
0x400–0x5FF
0x600–0x7FF
Composite Memory Select (CMS)
The ADSP-2188M has a programmable memory select signal that
is useful for generating memory select signals for memories
mapped to more than one space. The CMS signal is gener-
ated to have the same timing as each of the individual memory
select signals (PMS, DMS, BMS, IOMS) but can combine their
functionality.
Each bit in the CMSSEL register, when set, causes the CMS
signal to be asserted when the selected memory select is
asserted. For example, to use a 32K word memory to act as both
program and data memory, set the PMS and DMS bits in the
CMSSEL register and use the CMS pin to drive the chip
select of the memory, and use either DMS or PMS as the
additional address bit.
The CMS pin functions like the other memory select signals
with the same timing and bus request logic. A 1 in the enable bit
causes the assertion of the CMS signal at the same time as the
selected memory select signal. All enable bits default to 1 at reset,
except the BMS bit.
Byte Memory Select (BMS)
The ADSP-2188M’s BMS disable feature combined with the
CMS pin allows use of multiple memories in the byte memory
space. For example, an EPROM could be attached to the BMS
select, and an SRAM could be connected to CMS. Because at
reset BMS is enabled, the EPROM would be used for booting.
After booting, software could disable BMS and set the CMS
signal to respond to BMS, enabling the SRAM.
Byte Memory
The byte memory space is a bidirectional, 8-bit-wide, external
memory space used to store programs and data. Byte memory is
accessed using the BDMA feature. The byte memory space con-
sists of 256 pages, each of which is 16K × 8.
ADSP-2188M
Wait State Register
IOWAIT0 and Wait State Mode Select Bit
IOWAIT1 and Wait State Mode Select Bit
IOWAIT2 and Wait State Mode Select Bit
IOWAIT3 and Wait State Mode Select Bit
Table V. Wait States
The byte memory space on the ADSP-2188M supports read and
write operations as well as four different data formats. The byte
memory uses data bits 15:8 for data. The byte memory uses data
bits 23:16 and address bits 13:0 to create a 22-bit address. This
allows up to a 4 meg × 8 (32 megabit) ROM or RAM to be used
without glue logic. All byte memory accesses are timed by the
BMWAIT register and the wait state mode bit.
Byte Memory DMA (BDMA, Full Memory Mode)
The byte memory DMA controller allows loading and storing of
program instructions and data using the byte memory space. The
BDMA circuit is able to access the byte memory space while the
processor is operating normally and steals only one DSP cycle
per 8-, 16- or 24-bit word transferred.
The BDMA circuit supports four different data formats that are
selected by the BTYPE register field. The appropriate number
of 8-bit accesses are done from the byte memory space to build
the word size selected. Table VI shows the data formats sup-
ported by the BDMA circuit.
BTYPE
00
01
10
11
Unused bits in the 8-bit data memory formats are filled with 0s.
The BIAD register field is used to specify the starting address
for the on-chip memory involved with the transfer. The 14-bit
BEAD register specifies the starting address for the external byte
memory space. The 8-bit BMPAGE register specifies the start-
ing page for the external byte memory space. The BDIR register
field selects the direction of the transfer. Finally, the 14-bit
BWCOUNT register specifies the number of DSP words to
transfer and initiates the BDMA circuit transfers.
BDMA accesses can cross page boundaries during sequential
addressing. A BDMA interrupt is generated on the completion
of the number of transfers specified by the BWCOUNT register.
The BWCOUNT register is updated after each transfer so it can
be used to check the status of the transfers. When it reaches zero,
the transfers have finished and a BDMA interrupt is generated.
The BMPAGE and BEAD registers must not be accessed by the
DSP during BDMA operations.
The source or destination of a BDMA transfer will always be
on-chip program or data memory.
15 14 13 12 11 10 9
0
0
0
Internal Memory Space Word Size Alignment
Program Memory
Data Memory
Data Memory
Data Memory
BMPAGE
0
0
0
Table VI. Data Formats
BDMA CONTROL
0
8
0
7
0
OVERLAY
6
0
BDMA
BITS
5
0
4
0
3
1
24
16
8
8
2
0
BCR
0 = RUN DURING BDMA
1 = HALT DURING BDMA
BTYPE
1
0
BDIR
0 = LOAD FROM BM
1 = STORE TO BM
0
0
DM (0x3FE3)
Full Word
Full Word
MSBs
LSBs