ADSP-2188NBCA-320 Analog Devices Inc, ADSP-2188NBCA-320 Datasheet - Page 38
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ADSP-2188NBCA-320
Manufacturer Part Number
ADSP-2188NBCA-320
Description
IC DSP 16BIT 80MHZ 144CSPBGA
Manufacturer
Analog Devices Inc
Series
ADSP-21xxr
Type
Fixed Pointr
Datasheet
1.ADSP-2185NKSTZ-320.pdf
(48 pages)
Specifications of ADSP-2188NBCA-320
Rohs Status
RoHS non-compliant
Interface
Host Interface, Serial Port
Clock Rate
80MHz
Non-volatile Memory
External
On-chip Ram
256kB
Voltage - I/o
1.8V, 2.5V, 3.3V
Voltage - Core
1.90V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
144-CSPBGA
Device Core Size
16b
Architecture
Enhanced Harvard
Format
Fixed Point
Clock Freq (max)
80MHz
Mips
80
Device Input Clock Speed
80MHz
Ram Size
256KB
Operating Supply Voltage (typ)
2.5/3.3V
Operating Supply Voltage (min)
1.8V
Operating Supply Voltage (max)
2/3.6V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
144
Package Type
CSPBGA
Lead Free Status / Rohs Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ADSP-2188NBCA-320
Manufacturer:
SEMIKRON
Quantity:
230
ADSP-218xN
IDMA Read, Short Read Cycle
Table 25. IDMA Read, Short Read Cycle
1
2
3
4
5
6
Parameter
Timing Requirements:
t
t
t
Switching Characteristics:
t
t
t
t
t
Short Read Only must be disabled in the IDMA overlay memory mapped register. This mode is disabled by clearing (=0) Bit 14 of the IDMA overlay register, and is
Consider using the Short Read Only mode, instead, because Short Read mode is not applicable at high clock frequencies.
Start of Read = IS Low and IRD Low.
DM Read or first half of PM Read.
Second half of PM Read.
End of Read = IS High or IRD High.
IKR
IRP1
IRP2
IKHR
IKDH
IKDD
IRDE
IRDV
disabled by default upon reset.
1, 2
IACK Low Before Start of Read
Duration of Read (DM/PM1)
Duration of Read (PM2)
IACK High After Start of Read
IAD15–0 Data Hold After End of Read
IAD15–0 Data Disabled After End of Read
IAD15–0 Previous Data Enabled After Start of Read
IAD15–0 Previous Data Valid After Start of Read
IAD15–0
IACK
IRD
5
IS
4
3
3
Figure 36. IDMA Read, Short Read Cycle
t
IKR
Rev. A | Page 38 of 48 | August 2006
t
IRDE
6
6
t
t
IKHR
IRDV
t
IRP
PREVIOUS
DATA
t
IKDD
Min
0
10
10
0
0
t
IKDH
Max
2t
t
10
10
10
CK
CK
– 5
– 5
ns
Unit
ns
ns
ns
ns
ns
ns
ns