ADSP-21369KSZ-1A Analog Devices Inc, ADSP-21369KSZ-1A Datasheet - Page 4

• Manufacturer Part Number: ADSP-21369KSZ-1A
• Description: IC DSP 32BIT 266 MHZ 208-MQFP
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Floating Pointr

Specifications of ADSP-21369KSZ-1A

• Interface: DAI, DPI
• Clock Rate: 266MHz
• Non-volatile Memory: ROM (768 kB)
• On-chip Ram: 256kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.20V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 208-MQFP, 208-PQFP
• Device Core Size: 32/40Bit
• Architecture: Super Harvard
• Format: Floating Point
• Clock Freq (max): 266MHz
• Mips: 266
• Device Input Clock Speed: 266MHz
• Ram Size: 256KB
• Program Memory Size: 768KB
• Operating Supply Voltage (typ): 1.2/3.3V
• Operating Supply Voltage (min): 1.14/3.13V
• Operating Supply Voltage (max): 1.26/3.47V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: MQFP
• For Use With: ADZS-21369-EZLITE - KIT EVAL EZ LITE ADDS-21369
• Lead Free Status / Rohs Status: Compliant
• Other names: Q2886718

ADSP-21367/ADSP-21368/ADSP-21369
The block diagram of the ADSP-21368
peripheral clock domain (also known as the I/O processor) and
contains the following features:
• IOD0 (peripheral DMA) and IOD1 (external port DMA)
• Peripheral and external port buses for core connection
• External port with an AMI and SDRAM controller
• 4 units for PWM control
• 1 MTM unit for internal-to-internal memory transfers
• Digital applications interface that includes four precision
buses for 32-bit data transfers
clock generators (PCG), a input data port (IDP) for serial
and parallel interconnect, an S/PDIF receiver/transmitter,
four asynchronous sample rate converters, eight serial
ports, a flexible signal routing unit (DAI SRU).
80-BIT
MRF
S
SIMD Core
MULTIPLIER
DAG1
16x32
DMD/PMD 64
80-BIT
MRB
SHIFTER
on Page 1
DAG2
16x32
ALU
also shows the
JTAG
Figure 2. SHARC Core Block Diadram
Rev. E | Page 4 of 60 | July 2009
16x40-BIT
ASTATx
STYKx
Rx/Fx
PEx
RF
FLAG
PROGRAM SEQUENCER
TIMER
5 STAGE
DATA
SWAP
INTERRUPT
SHARC FAMILY CORE ARCHITECTURE
The ADSP-21367/ADSP-21368/ADSP-21369 are code compati-
ble at the assembly level with the ADSP-2126x, ADSP-21160,
and ADSP-21161, and with the first generation ADSP-2106x
SHARC processors. The ADSP-21367/ADSP-21368/
ADSP-21369 processors share architectural features with the
ADSP-2126x and ADSP-2116x SIMD SHARC processors, as
shown in
16x40-BIT
ASTATy
Sx/SFx
STYKy
• Digital peripheral interface that includes three timers, a 2-
PEy
RF
wire interface, two UARTs, two serial peripheral interfaces
(SPI), 2 precision clock generators (PCG) and a flexible sig-
nal routing unit (DPI SRU).
CACHE
Figure 2
PM ADDRESS 32
DM ADDRESS 32
PM DATA 64
DM DATA 64
ALU
and detailed in the following sections.
PM ADDRESS 24
PM DATA 48
SHIFTER
80-BIT
MSB
MULTIPLIER
SYSTEM
4x32-BIT
USTAT
64-BIT
PX
I/F
80-BIT
MSF