ADSP-21369KSZ-1A Analog Devices Inc, ADSP-21369KSZ-1A Datasheet - Page 44

• Manufacturer Part Number: ADSP-21369KSZ-1A
• Description: IC DSP 32BIT 266 MHZ 208-MQFP
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Floating Pointr

Specifications of ADSP-21369KSZ-1A

• Interface: DAI, DPI
• Clock Rate: 266MHz
• Non-volatile Memory: ROM (768 kB)
• On-chip Ram: 256kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.20V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 208-MQFP, 208-PQFP
• Device Core Size: 32/40Bit
• Architecture: Super Harvard
• Format: Floating Point
• Clock Freq (max): 266MHz
• Mips: 266
• Device Input Clock Speed: 266MHz
• Ram Size: 256KB
• Program Memory Size: 768KB
• Operating Supply Voltage (typ): 1.2/3.3V
• Operating Supply Voltage (min): 1.14/3.13V
• Operating Supply Voltage (max): 1.26/3.47V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: MQFP
• For Use With: ADZS-21369-EZLITE - KIT EVAL EZ LITE ADDS-21369
• Lead Free Status / Rohs Status: Compliant
• Other names: Q2886718

ADSP-21367/ADSP-21368/ADSP-21369
S/PDIF Receiver
The following section describes timing as it relates to the
S/PDIF receiver.
Internal Digital PLL Mode
In the internal digital phase-locked loop mode the internal PLL
(digital PLL) generates the 512 × FS clock.
Table 39. S/PDIF Receiver Internal Digital PLL Mode Timing
1
Parameter
Switching Characteristics
t
t
t
t
t
SCLK frequency is 64 × FS where FS = the frequency of LRCLK.
DFSI
HOFSI
DDTI
HDTI
SCLKIW
1
LRCLK Delay After SCLK
LRCLK Hold After SCLK
Transmit Data Delay After SCLK
Transmit Data Hold After SCLK
Transmit SCLK Width
(DATA CHANNEL
DAI_P20–1
DAI_P20–1
DAI_P20–1
(SCLK)
A/B)
(FS)
Figure 34. S/PDIF Receiver Internal Digital PLL Mode Timing
DRIVE EDGE
t
t
HOFSI
Rev. E | Page 44 of 60 | July 2009
HDTI
t
t
DDTI
DFSI
t
SCLKIW
Min
–2
–2
40
SAMPLE EDGE
5
Max
5
Unit
ns
ns
ns
ns
ns