ADSP-21375KSZ-2B Analog Devices Inc, ADSP-21375KSZ-2B Datasheet - Page 15

• Manufacturer Part Number: ADSP-21375KSZ-2B
• Description: IC DSP 32BIT 266MHZ 208-MQFP
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Floating Pointr

Specifications of ADSP-21375KSZ-2B

• Interface: DAI, DPI
• Clock Rate: 266MHz
• Non-volatile Memory: ROM (256 kB)
• On-chip Ram: 64kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.20V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 208-MQFP, 208-PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DATA MODES, ADSP-21371
For the ADSP-21371, the 32 data pins of the external memory
interface are muxed (using bits in the SYSCTL register) to sup-
port the external memory interface data (input/output), the
PDAP (input only), and the FLAGS (input/output).
provides the pin settings.
Table 7. ADSP-21371, Function of Data Pins
1
DATA MODES, ADSP-21375
For the ADSP-21375, the 16 data pins of the external memory
interface are muxed (using bits in the SYSCTL register) to sup-
port the external memory interface data (input/output), the
PDAP (input only) (PDAP for ADSP-21371), and the FLAGS
(input/output).
Table 8. ADSP-21375, Function of Data Pins
BOOT MODES
Table 9. Boot Mode Selection
DATA PIN MODE
000
001
010
011
100
101
110
111
These signals can be FLAGS or PWM or a mix of both. However, they can be selected only in groups of four. Their function is determined by the control signals
DATA PIN MODE
000
001
010
011
100
101
110
111
BOOTCFG1–0
00
01
10
11
FLAGS/PWM_SEL. For more information, see the ADSP-2136x SHARC Processor Hardware Reference for the ADSP-21367/8/9 Processors.
Table 8
provides the pin settings.
Booting Mode
SPI Slave Boot
SPI Master Boot
EPROM/FLASH Boot
Reserved
FLAGS/PWM15–0
FLAGS/PWM15–0
FLAGS/PWM15–0
DATA31–16
FLAGS15–8
DATA15–0
Table 7
PDAP (DATA + CTRL)
PDAP (DATA + CTRL)
Rev. B | Page 15 of 52 | June 2008
1
1
1
Three-state all pins
Three-state all pins
CORE INSTRUCTION RATE TO CLKIN RATIO MODES
For details on processor timing, see
Figure 3 on Page
Table 10. Core Instruction Rate/CLKIN Ratio Selection
CLKCFG1–0
00
01
10
11
EPDATA32–0
EPDATA15–0
EPDATA15-0
FLAG15–0
Reserved
Reserved
FLAGS15–8
DATA15–8
18.
ADSP-21371/ADSP-21375
Core to CLKIN Ratio
6:1
32:1
16:1
Reserved
EPDATA15–0
FLAGS15–0
EPDATA7–0
EPDATA7–0
FLAGS7–0
DATA7–0
Timing Specifications
EPDATA7–0
EPDATA7–0
FLAGS7–0
DATA7–0
and