ADSP-21375KSZ-2B Analog Devices Inc, ADSP-21375KSZ-2B Datasheet - Page 46

• Manufacturer Part Number: ADSP-21375KSZ-2B
• Description: IC DSP 32BIT 266MHZ 208-MQFP
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Floating Pointr

Specifications of ADSP-21375KSZ-2B

• Interface: DAI, DPI
• Clock Rate: 266MHz
• Non-volatile Memory: ROM (256 kB)
• On-chip Ram: 64kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.20V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 208-MQFP, 208-PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADSP-21371/ADSP-21375
OUTPUT DRIVE CURRENTS
Figure 34
ers of the ADSP-21371/ADSP-21375. The curves represent the
current drive capability of the output drivers as a function of
output voltage.
TEST CONDITIONS
The ac signal specifications (timing parameters) appear in
Table 17 on Page 22
output disable time, output enable time, and capacitive loading.
The timing specifications for the SHARC apply for the voltage
reference levels in
Timing is measured on signals when they cross the 1.5 V level as
described in
sured between the point that the first signal reaches 1.5 V and
the point that the second signal reaches 1.5 V.
Figure 34. ADSP-21371/ADSP-21375 Typical Drive at Junction Temperature
- 20
- 30
- 40
- 10
40
30
20
10
OUTPUT
0
Figure 35. Equivalent Device Loading for AC Measurements
0
OUTPUT
Figure 36. Voltage Reference Levels for AC Measurements
PIN
TO
INPUT
shows typical I-V characteristics for the output driv-
OR
V
Figure
OL
0.5
1.5V
Figure
3.47V, - 45°C
36. All delays (in nanoseconds) are mea-
SWEEP (V
through
1.0
(Includes All Fixtures)
35.
3.11V, 125°C
1.5
DDEXT
Table 43 on Page
30pF
) VOLTAGE (V)
2.0
V
OH
3.11V, 125°C
50
2.5
3.3V, 25°C
45. These include
3.0
3.3V, 25°C
Rev. B | Page 46 of 52 | June 2008
3.47V, -45°C
1.5V
3.5
1.5V
CAPACITIVE LOADING
Output delays and holds are based on standard capacitive loads:
30 pF on all pins (see
how output delays and holds vary with load capacitance. The
graphs of
outside the ranges shown for Typical Output Delay vs. Load
Capacitance and Typical Output Rise Time (20% to 80%,
V = Min) vs. Load Capacitance.
12
10
0
12
10
8
6
4
2
Figure
Figure 37. Typical Output Rise/Fall Time (20% to 80%,
Figure 38. Typical Output Rise/Fall Time (20% to 80%,
8
4
6
2
0
0
0
37,
y = 0.0467x + 1.6323
50
Figure
y = 0.049x + 1.5105
50
Figure
LOAD CAPACITANCE (pF)
V
LOAD CAPACITANCE (pF)
V
38, and
DDEXT
DDEXT
35).
100
100
y = 0.045x + 1.524
y = 0.0482x + 1.4604
= Max)
= Min)
Figure 39
Figure 39
RISE
150
150
RISE
shows graphically
FALL
FALL
may not be linear
200
200
250
250