EP1K100QC208-1N Altera, EP1K100QC208-1N Datasheet - Page 37
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EP1K100QC208-1N
Manufacturer Part Number
EP1K100QC208-1N
Description
IC ACEX 1K FPGA 100K 208-PQFP
Manufacturer
Altera
Series
ACEX-1K®r
Datasheet
1.EP1K10TC100-3N.pdf
(86 pages)
Specifications of EP1K100QC208-1N
Number Of Logic Elements/cells
4992
Number Of Labs/clbs
624
Total Ram Bits
49152
Number Of I /o
147
Number Of Gates
257000
Voltage - Supply
2.375 V ~ 2.625 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
208-MQFP, 208-PQFP
Logic Type
Programmable Logic Device (PLD)
No. Of I/o's
147
Frequency
180MHz
Supply Current Max
25mA
Operating Temperature Range
0°C To +70°C
Logic Case Style
QFP
No. Of Pins
208
Rohs Compliant
Yes
Family Name
ACEX™ 1K
Number Of Usable Gates
100000
Number Of Logic Blocks/elements
4992
# I/os (max)
147
Frequency (max)
333.33MHz
Process Technology
CMOS
Operating Supply Voltage (typ)
2.5V
Logic Cells
4992
Ram Bits
49152
Device System Gates
257000
Operating Supply Voltage (min)
2.375V
Operating Supply Voltage (max)
2.625V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
208
Package Type
PQFP
Clock Management
PLL
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-1823
EP1K100QC208-1N
EP1K100QC208-1N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP1K100QC208-1N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Altera Corporation
Figure 19. Specifications for the Incoming & Generated Clocks
Note:
(1)
The t
period.
I
ClockLock
Generated
Clock
parameter refers to the nominal input clock period; the t
Input
Clock
t
R
For designs that require both a multiplied and non-multiplied clock, the
clock trace on the board can be connected to the GCLK1 pin. In the Altera
software, the GCLK1 pin can feed both the ClockLock and ClockBoost
circuitry in the ACEX 1K device. However, when both circuits are used,
the other clock pin cannot be used.
ClockLock & ClockBoost Timing Parameters
For the ClockLock and ClockBoost circuitry to function properly, the
incoming clock must meet certain requirements. If these specifications are
not met, the circuitry may not lock onto the incoming clock, which
generates an erroneous clock within the device. The clock generated by
the ClockLock and ClockBoost circuitry must also meet certain
specifications. If the incoming clock meets these requirements during
configuration, the ClockLock and ClockBoost circuitry will lock onto the
clock during configuration. The circuit will be ready for use immediately
after configuration.
specifications.
t
OUTDUTY
t
CLK1
t
F
t
INDUTY
t
t
O
O
ACEX 1K Programmable Logic Device Family Data Sheet
Figure 19
t
I +
t
O +
t
INCLKSTB
t
JITTER
shows the incoming and generated clock
O
parameter refers to the nominal output clock
t
Note (1)
O
t
JITTER
t
I +
t
CLKDEV
37
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