EP1K100QC208-1N Altera, EP1K100QC208-1N Datasheet - Page 57
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EP1K100QC208-1N
Manufacturer Part Number
EP1K100QC208-1N
Description
IC ACEX 1K FPGA 100K 208-PQFP
Manufacturer
Altera
Series
ACEX-1K®r
Datasheet
1.EP1K10TC100-3N.pdf
(86 pages)
Specifications of EP1K100QC208-1N
Number Of Logic Elements/cells
4992
Number Of Labs/clbs
624
Total Ram Bits
49152
Number Of I /o
147
Number Of Gates
257000
Voltage - Supply
2.375 V ~ 2.625 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
208-MQFP, 208-PQFP
Logic Type
Programmable Logic Device (PLD)
No. Of I/o's
147
Frequency
180MHz
Supply Current Max
25mA
Operating Temperature Range
0°C To +70°C
Logic Case Style
QFP
No. Of Pins
208
Rohs Compliant
Yes
Family Name
ACEX™ 1K
Number Of Usable Gates
100000
Number Of Logic Blocks/elements
4992
# I/os (max)
147
Frequency (max)
333.33MHz
Process Technology
CMOS
Operating Supply Voltage (typ)
2.5V
Logic Cells
4992
Ram Bits
49152
Device System Gates
257000
Operating Supply Voltage (min)
2.375V
Operating Supply Voltage (max)
2.625V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
208
Package Type
PQFP
Clock Management
PLL
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-1823
EP1K100QC208-1N
EP1K100QC208-1N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP1K100QC208-1N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Altera Corporation
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t
t
t
t
t
t
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t
t
t
t
t
t
EABAA
EABRCCOMB
EABRCREG
EABWP
EABWCCOMB
EABWCREG
EABDD
EABDATACO
EABDATASU
EABDATAH
EABWESU
EABWEH
EABWDSU
EABWDH
EABWASU
EABWAH
EABWO
Table 25. EAB Timing Macroparameters
Symbol
EAB address access delay
EAB asynchronous read cycle time
EAB synchronous read cycle time
EAB write pulse width
EAB asynchronous write cycle time
EAB synchronous write cycle time
EAB data-in to data-out valid delay
EAB clock-to-output delay when using output registers
EAB data/address setup time before clock when using input register
EAB data/address hold time after clock when using input register
EAB WE setup time before clock when using input register
EAB WE hold time after clock when using input register
EAB data setup time before falling edge of write pulse when not using input
registers
EAB data hold time after falling edge of write pulse when not using input
registers
EAB address setup time before rising edge of write pulse when not using
input registers
EAB address hold time after falling edge of write pulse when not using input
registers
EAB write enable to data output valid delay
Notes
Parameter
ACEX 1K Programmable Logic Device Family Data Sheet
(1),
(6)
Conditions
57
13