EP3C55F484C8N Altera, EP3C55F484C8N Datasheet - Page 121

• Manufacturer Part Number: EP3C55F484C8N
• Description: IC CYCLONE III FPGA 55K 484FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C55F484C8N

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2396160
• Number Of I /o: 327
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 55856
• # I/os (max): 327
• Frequency (max): 402MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 55856
• Ram Bits: 2396160
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• No. Of Logic Blocks: 3491
• Family Type: Cyclone III
• No. Of I/o's: 327
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 402MHz
• Operating Temperature Range: 0°C To +85°C
• Rohs Compliant: Yes
• For Use With: 544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2510

Chapter 6: I/O Features in the Cyclone III Device Family
Pad Placement and DC Guidelines
Pad Placement and DC Guidelines
Pad Placement
DC Guidelines
Chapter Revision History
Table 6–7. Chapter Revision History (Part 1 of 3)
© December 2009
December 2009
July 2009
June 2009
October 2008
Date
f
Altera Corporation
Altera recommends that you create a Quartus II design, enter your device I/O
assignments, and compile your design to validate your pin placement. The Quartus II
software checks your pin connections with respect to the I/O assignment and
placement rules to ensure proper device operation. These rules are dependent on
device density, package, I/O assignments, voltage assignments, and other factors that
are not fully described in this chapter.
For more information about how the Quartus II software checks I/O restrictions, refer
to the
For the Quartus II software to automatically check for illegally placed pads according
to the DC guidelines, set the DC current sink or source value to Electromigration
Current assignment on each of the output pins that are connected to the external
resistive load.
The programmable current strength setting has an impact on the amount of DC
current that an output pin can source or sink. Determine if the current strength setting
is sufficient for the external resistive load condition on the output pin.
Table 6–7
Version
3.2
3.1
3.0
2.1
I/O Management
lists the revision history for this chapter.
Minor changes to the text.
Made minor correction to the part number.
Updated to include Cyclone III LS information
■
■
■
■
■
■
■
■
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Updated chapter part number.
Updated “Introduction” on page 6–1, “PCI-Clamp Diode” on page 6–6, “On-
Chip Series Termination Without Calibration” on page 6–10, “I/O Standards”
on page 6–11, “I/O Banks” on page 6–16, “High-Speed Differential
Interfaces” on page 6–20, and “External Memory Interfacing” on page 6–20.
Updated Table 6–6 on page 6–18.
Added (Note 6) to Table 6–5.
Updated the “I/O Banks” section.
Updated the “Differential Pad Placement Guidelines” section.
Updated the “V
Removed any mention of “RSDS and PPDS are registered trademarks of
National Semiconductor” from chapter.
Updated chapter to new template.
chapter in volume 2 of the Quartus II Handbook.
REF
Pad Placement Guidelines” section.
Changes Made
Cyclone III Device Handbook, Volume 1
6–21