EP3C55F484C8N Altera, EP3C55F484C8N Datasheet - Page 136

• Manufacturer Part Number: EP3C55F484C8N
• Description: IC CYCLONE III FPGA 55K 484FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C55F484C8N

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2396160
• Number Of I /o: 327
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 55856
• # I/os (max): 327
• Frequency (max): 402MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 55856
• Ram Bits: 2396160
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• No. Of Logic Blocks: 3491
• Family Type: Cyclone III
• No. Of I/o's: 327
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 402MHz
• Operating Temperature Range: 0°C To +85°C
• Rohs Compliant: Yes
• For Use With: 544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2510

7–12
Figure 7–7. RSDS Interface with Single Resistor Network on the Top and Bottom I/O Banks
Note to
(1)
LVPECL I/O Support in the Cyclone III Device Family
Figure 7–8. LVPECL AC-Coupled Termination
Cyclone III Device Handbook, Volume 1
R
P
Figure
= 100
Ω
7–7:
f
Cyclone III Device Family
RSDS Transmitter
Figure 7–7
bottom I/O banks.
The LVPECL I/O standard is a differential interface standard that requires a 2.5-V
V
telecommunications, data communications, and clock distribution. The Cyclone III
device family supports the LVPECL input standard at the dedicated clock input pins
only. The LVPECL receiver requires an external 100-Ω termination resistor between
the two signals at the input buffer.
For more information about the LVPECL I/O standard electrical specification, refer to
the
AC coupling is required when the LVPECL common mode voltage of the output
buffer is higher than the Cyclone III device family LVPECL input common mode
voltage.
Figure 7–8
receiver are external to the device. DC-coupled LVPECL is supported if the LVPECL
output common mode voltage is in the Cyclone III device family LVPECL input buffer
specification
CCIO.
Emulated
Cyclone III Device Data Sheet
Transmitter
LVPECL
This standard is used in applications involving video graphics,
shows the RSDS interface with a single resistor network on the top and
shows the AC-coupled termination scheme. The 50-Ω resistors used at the
(Figure
Single Resistor Network
0.1 µF
0.1 µF
7–9).
R
P
Chapter 7: High-Speed Differential Interfaces in the Cyclone III Device Family
Z 0 = 50
Z 0 = 50
and
Cyclone III LS Device Data Sheet
V ICM
50 Ω
50 Ω
50
50
100 Ω
Cyclone III Device Family
LVPECL Receiver
RSDS Receiver
© December 2009 Altera Corporation
High-Speed I/O Standards Support
chapters.