EP2C70F672C8N Altera, EP2C70F672C8N Datasheet - Page 51

• Manufacturer Part Number: EP2C70F672C8N
• Description: IC CYCLONE II FPGA 70K 672-FBGA
• Manufacturer: Altera
• Series: Cyclone® IIr

Specifications of EP2C70F672C8N

• Number Of Logic Elements/cells: 68416
• Number Of Labs/clbs: 4276
• Total Ram Bits: 1152000
• Number Of I /o: 422
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-FBGA
• No. Of Logic Blocks: 4276
• Family Type: Cyclone II
• No. Of I/o's: 422
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 320MHz
• Operating Temperature Range: 0°C To +85°C
• Rohs Compliant: Yes
• Family Name: Cyclone® II
• Number Of Logic Blocks/elements: 68416
• # I/os (max): 422
• Frequency (max): 402.58MHz
• Process Technology: 90nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 68416
• Ram Bits: 1152000
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 672
• Package Type: FBGA
• For Use With: P0304 - DE2-70 CALL FOR ACADEMIC PRICING544-1703 - VIDEO KIT W/CYCLONE II EP2C70N544-1699 - DSP KIT W/CYCLONE II EPS2C70N
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-1688

Figure 2–21. Row I/O Block Connection to the Interconnect
Notes to
(1)
(2)
Altera Corporation
February 2007
The 35 data and control signals consist of five data out lines, io_dataout[4..0], five output enables,
io_coe[4..0], five input clock enables, io_cce_in[4..0], five output clock enables, io_cce_out[4..0],
five clocks, io_cclk[4..0], five asynchronous clear signals, io_caclr[4..0], and five synchronous clear
signals, io_csclr[4..0].
Each of the five IOEs in the row I/O block can have two io_datain (combinational or registered) inputs.
LAB Local
Interconnect
R4 & R24 Interconnects
Figure
to Adjacent LAB
Interconnect
Direct Link
2–21:
LAB
io_datain0[4..0]
io_datain1[4..0] (2)
C4 Interconnects
from Adjacent LAB
Interconnect
Direct Link
I/O Block Local
Interconnect
io_clk[5..0]
35
Cyclone II Device Handbook, Volume 1
I/O Block
Contains up to
Row I/O Block
Row
Five IOEs
Cyclone II Architecture
35 Data and
Control Signals
from Logic Array (1)
2–39