EP1S20F672C7 Altera, EP1S20F672C7 Datasheet - Page 149

• Manufacturer Part Number: EP1S20F672C7
• Description: IC STRATIX FPGA 20K LE 672-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S20F672C7

• Number Of Logic Elements/cells: 18460
• Number Of Labs/clbs: 1846
• Total Ram Bits: 1669248
• Number Of I /o: 426
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 18460
• # I/os (max): 426
• Frequency (max): 420.17MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 18460
• Ram Bits: 1669248
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 672
• Package Type: FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 544-1113

Altera Corporation
July 2005
1,020-pin
FineLine
BGA
1,508-pin
FineLine
BGA
956-pin
BGA
1,020-pin
FineLine
BGA
Table 2–40. EP1S60 Differential Channels (Part 2 of 2)
Table 2–41. EP1S80 Differential Channels (Part 1 of 2)
Package
Package
Transmitter/
Transmitter
(4)
Receiver
Transmitter
(4)
Receiver
Transmitter
(4)
Receiver
Transmitter
(4)
Receiver
Transmitter/
Receiver
Receiver
80 (12)
(7)
80 (10)
(7)
80 (36)
(7)
80 (36)
(7)
Channels
80 (40)
(7)
80
92 (12)
(7)
90 (10)
(7)
Channels
Total
Total
840
840
840
840
840
840
840
840
Maximum
840
840
840
840
840
840
840
840
Maximum
(Mbps)
(Mbps)
Speed
Speed
(5)
(5)
(5)
(5)
(5)
(5)
(5)
(5)
,
,
,
,
,
,
,
,
(8)
(8)
(8)
(8)
(8)
(8)
(8)
(8)
PLL1 PLL2 PLL3 PLL4 PLL7 PLL8 PLL9 PLL10
PLL1 PLL2 PLL3 PLL4 PLL7 PLL8 PLL9 PLL10
(18)
(2)
(6)
(8)
(2)
(6)
12
22
20
40
12
22
20
40
10
20
20
40
10
20
20
40
Center Fast PLLs
Center Fast PLLs
Note (1)
Note (1)
(10)
(18)
(4)
(6)
(4)
(6)
10
22
20
40
10
22
20
40
10
20
20
40
10
20
20
40
(10)
(18)
(4)
(6)
(4)
(6)
10
22
20
40
10
22
20
40
10
20
20
40
10
20
20
40
Stratix Device Handbook, Volume 1
(18)
(2)
(6)
(8)
(2)
(6)
12
22
20
40
12
22
20
40
10
20
20
40
10
20
20
40
20
20
12
(8)
12
(8)
20
20
(8)
12
(8)
20
20
10
10
20
20
10
(2)
10
(2)
12
Corner Fast PLLs (2),
Corner Fast PLLs (2),
(10)
(10)
(10)
(10)
Stratix Architecture
(3)
(3)
20
20
10
10
20
20
10
10
20
20
10
10
20
20
10
10
10 (3)
10 (3)
(10)
(10)
(10)
(10)
20
20
10
10
20
20
10
10
20
20
10
10
20
20
12 (8)
12 (8)
12 (8)
12 (8)
10 (2)
10 (2)
2–135
20
20
20
20
(3)
(3)
20
20
10
10
20
20