EP1S20F672C7 Altera, EP1S20F672C7 Datasheet - Page 17

• Manufacturer Part Number: EP1S20F672C7
• Description: IC STRATIX FPGA 20K LE 672-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S20F672C7

• Number Of Logic Elements/cells: 18460
• Number Of Labs/clbs: 1846
• Total Ram Bits: 1669248
• Number Of I /o: 426
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 18460
• # I/os (max): 426
• Frequency (max): 420.17MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 18460
• Ram Bits: 1669248
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 672
• Package Type: FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 544-1113

Logic Array
Blocks
Altera Corporation
July 2005
EP1S10
EP1S20
EP1S25
EP1S30
EP1S40
EP1S60
EP1S80
Table 2–1. Stratix Device Resources
Device
Columns/Blocks
M512 RAM
10 / 574
11 / 767
6 / 194
6 / 224
7 / 295
8 / 384
4 / 94
The number of M512 RAM, M4K RAM, and DSP blocks varies by device
along with row and column numbers and M-RAM blocks.
the resources available in Stratix devices.
Each LAB consists of 10 LEs, LE carry chains, LAB control signals, local
interconnect, LUT chain, and register chain connection lines. The local
interconnect transfers signals between LEs in the same LAB. LUT chain
connections transfer the output of one LE’s LUT to the adjacent LE for fast
sequential LUT connections within the same LAB. Register chain
connections transfer the output of one LE’s register to the adjacent LE’s
register within an LAB. The Quartus
within an LAB or adjacent LABs, allowing the use of local, LUT chain,
and register chain connections for performance and area efficiency.
Figure 2–2
Columns/Blocks
M4K RAM
3 / 138
3 / 171
3 / 183
4 / 292
4 / 364
2 / 60
2 / 82
shows the Stratix LAB.
M-RAM
Blocks
1
2
2
4
4
6
9
Columns/Blocks
DSP Block
®
2 / 10
2 / 10
2 / 12
2 / 14
2 / 18
2 / 22
2 / 6
II Compiler places associated logic
Stratix Device Handbook, Volume 1
Columns
LAB
101
40
52
62
67
77
90
Stratix Architecture
Table 2–1
LAB Rows
30
41
46
57
61
73
91
lists
2–3