EP2SGX30CF780C4N Altera, EP2SGX30CF780C4N Datasheet - Page 296
EP2SGX30CF780C4N
Manufacturer Part Number
EP2SGX30CF780C4N
Description
IC STRATIX II GX 30K 780-FBGA
Manufacturer
Altera
Series
Stratix® II GXr
Datasheet
1.EP2SGX30DF780C5.pdf
(316 pages)
Specifications of EP2SGX30CF780C4N
Number Of Logic Elements/cells
33880
Number Of Labs/clbs
1694
Total Ram Bits
1369728
Number Of I /o
361
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-1927
EP2SGX30CF780C4N
EP2SGX30CF780C4N
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High-Speed I/O
Specifications
t
f
J
W
t
t
Timing unit interval (TUI)
f
f
f
Channel-to-channel skew (TCCS)
Sampling window (SW)
Input jitter
Output jitter
t
t
C
H S C L K
R I S E
F A L L
IN
H S D R
H S D R D P A
DUTY
L O C K
High-Speed Timing Specifications
Table 4–106. High-Speed Timing Specifications and Definitions
Table 4–106
1.2-V HSTL
LVPECL
Column DDIO Output I/O
Table 4–105. Maximum DCD for DDIO Output on Column I/O Pins With PLL in
the Clock Path (Part 2 of 2)
Maximum DCD (ps) for
High-speed receiver/transmitter input and output clock period.
High-speed receiver/transmitter input and output clock frequency.
Deserialization factor (width of parallel data bus).
PLL multiplication factor.
Low-to-high transmission time.
High-to-low transmission time.
The timing budget allowed for skew, propagation delays, and data
sampling window. (TUI = 1/(Receiver Input Clock Frequency ×
Multiplication Factor) = t
Fast PLL input clock frequency
Maximum/minimum LVDS data transfer rate (f
Maximum/minimum LVDS data transfer rate (f
The timing difference between the fastest and the slowest output edges
including t
same fast PLL. The clock is included in the TCCS measurement.
The period of time during which the data must be valid in order to capture
it correctly. The setup and hold times determine the ideal strobe position
within the sampling window.
Peak-to-peak input jitter on high-speed PLLs.
Peak-to-peak output jitter on high-speed PLLs.
Duty cycle on high-speed transmitter output clock.
Lock time for high-speed transmitter and receiver PLLs.
Standard
provides high-speed timing specifications definitions.
CO
variation and clock skew across channels driven by the
Stratix II GX Devices (PLL Output Feeding
C
/w).
-3 Device
155
180
Definitions
DDIO)
-4 and -5 Device
H S D R
H S D R D PA
= 1/TUI), non-DPA.
155
180
= 1/TUI), DPA.
Unit
ps
ps
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