EP1AGX90EF1152I6N Altera, EP1AGX90EF1152I6N Datasheet - Page 217

• Manufacturer Part Number: EP1AGX90EF1152I6N
• Description: IC ARRIA GX FPGA 90K 1152FBGA
• Manufacturer: Altera
• Series: Arria GXr

Specifications of EP1AGX90EF1152I6N

• Number Of Logic Elements/cells: 90220
• Number Of Labs/clbs: 4511
• Total Ram Bits: 4477824
• Number Of I /o: 538
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1152-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2387

Chapter 4: DC and Switching Characteristics
Duty Cycle Distortion
Duty Cycle Distortion
© December 2009 Altera Corporation
Table 4–107. Arria GX Maximum Output Clock Rate for Dedicated Clock Pins (Part 4 of 4)
Duty cycle distortion (DCD) describes how much the falling edge of a clock is off from
its ideal position. The ideal position is when both the clock high time (CLKH) and the
clock low time (CLKL) equal half of the clock period (T), as shown in
DCD is the deviation of the non-ideal falling edge from the ideal falling edge, such as
D1 for the falling edge A and D2 for the falling edge B (refer to
maximum DCD for a clock is the larger value of D1 and D2.
1.5 V
SSTL-2 CLASS I
SSTL-2 CLASS II
SSTL-18 CLASS I
SSTL-18 CLASS II
1.8-V HSTL CLASS I
1.8-V HSTL CLASS II
1.5-V HSTL CLASS I
1.2-V HSTL
DIFFERENTIAL SSTL-2
DIFFERENTIAL 2.5-V
SSTL CLASS II
DIFFERENTIAL 1.8-V
SSTL CLASS I
DIFFERENTIAL 1.8-V
SSTL CLASS II
DIFFERENTIAL 1.8-V
HSTL CLASS I
DIFFERENTIAL 1.8-V
HSTL CLASS II
DIFFERENTIAL 1.5-V
HSTL CLASS I
DIFFERENTIAL 1.2-V
HSTL
I/O Standards
SERIES_50_OHMS
SERIES_50_OHMS
SERIES_25_OHMS
SERIES_50_OHMS
SERIES_25_OHMS
SERIES_50_OHMS
SERIES_50_OHMS
SERIES_50_OHMS
SERIES_25_OHMS
SERIES_50_OHMS
SERIES_25_OHMS
SERIES_50_OHMS
SERIES_25_OHMS
SERIES_50_OHMS
SERIES_50_OHMS
SERIES_50_OHMS
SERIES_25_OHMS
Drive Strength
–6 Speed Grade
373
467
467
327
420
561
420
467
233
467
467
327
420
561
420
467
233
Arria GX Device Handbook, Volume 1
Figure
Figure
4–10). The
Units
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
4–10.
4–95